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Xilinx PCI v3.0 manual Exemplar LeonardoSpectrum, 17 Options for Implementation

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Exemplar LeonardoSpectrum

Exemplar LeonardoSpectrum

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12.From the main project window, click Change Target to display the Options for Implementation dialog box, as shown in Figure 5-17.

Figure 5-17:Options for Implementation

13.On the Device tab, set the Technology, Part, Speed, and Package options to reflect the targeted device (a V300BG432-6 in this example). Be sure that Disable I/O Insertion is deselected.

14.On the Options/Constraints tab, deselect Symbolic FSM Compiler (leave Resource Sharing selected) and set the Frequency to 66 MHz.

15.On the Implementation Results tab, deselect Write Vendor Constraint File.

16.Click OK to return to the main project window; then click Run.

Synplify synthesizes the design and writes out an optimized EDIF file. In the lower-right corner of the window, the various stages or synthesis, such as Compiling or Mapping, are displayed. When the process is complete, Done is displayed. Note that Synplify may issue a number of warnings (which are expected) about instantiated I/O cells and attributes used for other synthesis tools.

Exemplar LeonardoSpectrum

Before attempting to synthesize a design, ensure that the Exemplar LeonardoSpectrum environment is properly configured for use.

1.Navigate to the synthesis directory:

cd <Install Path>/hdl/example/synthesis

The synthesis directory contains a script for use with LeonardoSpectrum.

2.Edit the script to change the following line:

cd <Install Path>/hdl/example/synthesis

Modify the path to point to the actual installation location, and then save the file.

3.Invoke LeonardoSpectrum.

4.Synthesize the design by running the script leonardo.tcl.

Note that if you run LeonardoSpectrum with the graphical user interface, the quicksetup form cannot be used to synthesize the design. Instead, choose File > Run Script from the menu.

PCI v3.0.151 Getting Started Guide

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UG157 August 31, 2005

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Xilinx PCI v3.0 manual Exemplar LeonardoSpectrum, 17 Options for Implementation

Contents

v3.0.151 UG157 August 31LogiCORE PCI Getting Started GuideVersion RevisionPCI v3.0.151 Getting Started Guide UG157 August 31 Document → PDF Setup VersionRevision UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 1 Getting Started Table of ContentsChapter 2 Installing and Licensing the Core Preface About This GuideISE Foundation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design Chapter 7 Timing SimulationGuide Contents About This GuidePreface Preface About This Guide Additional ResourcesConventions Typographicallowpwr =onoff Online DocumentConventions Italic fontPreface About This Guide PCI v3.0.151 Getting Started GuideUG157 August 31 Additional Documentation Getting StartedChapter About the Example DesignDocument Technical SupportFeedback PCI Interface CoreChapter Installing and Licensing the CoreInstalling the Core System RequirementsCORE Generator IP Updates Installer Manual Installation CORE Generator IP UpdateChapter 2 Installing and Licensing the Core Direct Download of Standalone Core Installing the CoreDirect Download Licensing OptionsEvaluation FullUG157 August 31 Installing Your License FileInstalling Your License File PCI v3.0.151 Getting Started GuideChapter 2 Installing and Licensing the Core PCI v3.0.151 Getting Started GuideUG157 August 31 Supported Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface Selection TableWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedTable 3-2 Guide File Information Wrapper FilesConstraints Files Guide FilesFigure 3-1 Sample SLOT64 Generation Device InitializationBus Width Detection Device Initialization Table 3-2 Guide File InformationDatapath Output Clock Enable Input Delay BuffersChapter 3 Family Specific Considerations Implementation Input Delay BuffersTable 3-3 Delay Buffer Settings Delay SettingChapter 3 Family Specific Considerations Regional Clock Usage64-bit Interfaces Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces PackageChapter 3 Family Specific Considerations Bus Clock UsageFF668 FF672Electrical Compliance Electrical Compliance3.3V PCI COMPLIANT Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION System SupplyGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation Chapter 3 Family Specific Considerations PCI v3.0.151 Getting Started GuideUG157 August 31 Functional Simulation Cadence NC-VerilogChapter Model Technology ModelSim VerilogChapter 4 Functional Simulation Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimChapter Synthesizing a DesignSynplicity Synplify Figure 5-5 Create a New ProjectChapter 5 Synthesizing a Design Figure 5-6 Main Project Window Figure 5-7 Select Files to Add LibrarySynplicity Install Path/lib/xilinx Synplicity Synplify Figure 5-8 Files to Add LogiCORE FilesFigure 5-9 Select Files to Add Dialog Box User Application Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a DesignFigure 5-11 Options for Implementation Device Synplicity Synplify16. Click OK to return to the main project window Chapter 5 Synthesizing a Design Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window VHDLSynplicity Synplify Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Install Path/vhdl/src/xpciChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Chapter 5 Synthesizing a Design Xilinx XSTImplementing a Design ISE FoundationChapter Chapter 6 Implementing a Design Cadence NC-Verilog Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v ChapterVHDL Chapter 7 Timing SimulationModel Technology ModelSim Verilogsource/pingtb.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhdChapter 7 Timing Simulation PCI v3.0.151 Getting Started GuideUG157 August 31