Xilinx PCI v3.0 Datapath Output Clock Enable, Input Delay Buffers, Family Specific Considerations

R

Chapter 3: Family Specific Considerations

Although this technique is not technically compliant with the PCI specification due to the extra loading on REQ64# and RST#, the use of a large series resistor helps minimize this effect. The inverter may be pushed into the FPGA.

An alternate method is to push the entire circuit into the FPGA and use the REQ64Q_N and RST signals provided to the user application. This method requires that the FPGA be fully configured by the rising edge of RST#.

When SLOT64 is deasserted, the PCI64 interface automatically three-states the 64-bit extension signals. In this situation, the 64-bit extension signals are undriven, which may result in additional power consumption by the input buffers.

If the additional power consumption is of concern due to design requirements, consider changing the “Disabled Extension Drive” option in the HDL configuration file. This option, when enabled, forces the PCI64 interface to actively drive the extension signals when SLOT64 is deasserted.

Note: Although this option may reduce power consumption, it creates an electrically objectionable situation. When a 64-bit card is installed in a 32-bit slot, the 64-bit bus extension is floating in free space and unprotected from roaming screwdrivers.

Datapath Output Clock Enable

The PCI interface targeting Virtex devices uses one of the following methods to generate and distribute the datapath output clock enable signal:

•Specialized device resources: the PCIIOBs, PCILOGIC, and PCI_CE

•Generic device resources: IOBs, LUTs, and general purpose routing

The specialized device resources offer higher and more predictable performance. However, they constrain the PCI interface to the left or right sides of the FPGA device, and limit the number of PCI interface instances to two. The generic device resources, while lower performance and less predictable, offer greater flexibility.

To summarize, the generic device resources must be used in the following cases:

•When the target device is Virtex-II, Virtex-II Pro, Virtex-4, or Spartan-3

•Where more than two instances of the interface are required

•When the interface cannot be located on the left or right side

To disable the use of specialized device resources, edit the HDL configuration file and set the CFG[251] bit to logic one. You must set CFG[251] to logic one to target a Virtex-II, Virtex-II Pro, Virtex-4, or Spartan-3 device. Use of this option with other devices is not supported, and is incompatible with the provided constraint and guide files.

Input Delay Buffers

Input delay buffers are used to provide guaranteed hold time on all bus inputs. Where possible, the PCI interface targeting Virtex devices uses input delay elements present in the

30	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005