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manual PCI v3.0.151 Getting Started Guide, UG157 August 31
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PCI v3.0.151 Getting Started Guide
www.xilinx.com
UG157 August 31, 2005
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Contents
UG157 August 31
LogiCORE PCI
Getting Started Guide
v3.0.151
Revision
Version
PCI v3.0.151 Getting Started Guide UG157 August 31
Version
Document → PDF Setup
Revision
PCI v3.0.151 Getting Started Guide
UG157 August 31
Table of Contents
Chapter 2 Installing and Licensing the Core
Preface About This Guide
Chapter 1 Getting Started
Chapter 5 Synthesizing a Design
Chapter 6 Implementing a Design
Chapter 7 Timing Simulation
ISE Foundation
About This Guide
Guide Contents
Preface
Additional Resources
Conventions
Typographical
Preface About This Guide
Online Document
Conventions
Italic font
lowpwr =onoff
PCI v3.0.151 Getting Started Guide
Preface About This Guide
UG157 August 31
Getting Started
Chapter
About the Example Design
Additional Documentation
Technical Support
Feedback
PCI Interface Core
Document
Installing and Licensing the Core
Installing the Core
System Requirements
Chapter
Manual Installation CORE Generator IP Update
CORE Generator IP Updates Installer
Chapter 2 Installing and Licensing the Core
Installing the Core
Direct Download of Standalone Core
Licensing Options
Evaluation
Full
Direct Download
Installing Your License File
Installing Your License File
PCI v3.0.151 Getting Started Guide
UG157 August 31
PCI v3.0.151 Getting Started Guide
Chapter 2 Installing and Licensing the Core
UG157 August 31
Family Specific Considerations
Design Support
Table 3-1 Device and Interface Selection Table
Supported
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Design Support
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Design Support
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Design Support
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Design Support
Table 3-1 Device and Interface Selection Table Continued
Supported
Wrapper File
Wrapper Files
Constraints Files
Guide Files
Table 3-2 Guide File Information
Device Initialization
Bus Width Detection
Device Initialization Table 3-2 Guide File Information
Figure 3-1 Sample SLOT64 Generation
Input Delay Buffers
Datapath Output Clock Enable
Chapter 3 Family Specific Considerations
Input Delay Buffers
Table 3-3 Delay Buffer Settings
Delay Setting
Implementation
Regional Clock Usage
Chapter 3 Family Specific Considerations
Regional Clock Usage
Table 3-4 Virtex-4 Device and Package 64-bit Interfaces
Package
64-bit Interfaces
Bus Clock Usage
FF668
FF672
Chapter 3 Family Specific Considerations
Electrical Compliance
Electrical Compliance
Figure 3-3 Relationship For 3.3V Input Buffer Compliance
REGION
System Supply
3.3V PCI COMPLIANT
Generating Bitstreams
Generating Bitstreams
Figure 3-4 Output Driver VCCO Generation
PCI v3.0.151 Getting Started Guide
Chapter 3 Family Specific Considerations
UG157 August 31
Cadence NC-Verilog
Functional Simulation
Chapter
Verilog
Model Technology ModelSim
Chapter 4 Functional Simulation
VHDL
Model Technology ModelSim
Install Path/vhdl/example/funcsim
Chapter 4 Functional Simulation
Synthesizing a Design
Synplicity Synplify
Figure 5-5 Create a New Project
Chapter
Figure 5-7 Select Files to Add Library
Chapter 5 Synthesizing a Design Figure 5-6 Main Project Window
Synplicity Install Path/lib/xilinx
Figure 5-8 Files to Add LogiCORE Files
Synplicity Synplify
Figure 5-9 Select Files to Add Dialog Box User Application
Chapter 5 Synthesizing a Design
Figure 5-10 Main Project Window with Source Files
Synplicity Synplify
Figure 5-11 Options for Implementation Device
16. Click OK to return to the main project window
Figure 5-12 Create a New Project
Figure 5-13 Main Project Window
VHDL
Chapter 5 Synthesizing a Design
Figure 5-14 Select Files to Add Library
Figure 5-15 Select Files to Add LogiCORE Files
Install Path/vhdl/src/xpci
Synplicity Synplify
Figure 5-16 Project Window with Source Files
Chapter 5 Synthesizing a Design
Exemplar LeonardoSpectrum
Exemplar LeonardoSpectrum
Figure 5-17 Options for Implementation
Xilinx XST
Chapter 5 Synthesizing a Design
ISE Foundation
Implementing a Design
Chapter
Chapter 6 Implementing a Design
Timing Simulation
cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v
Chapter
Cadence NC-Verilog
Chapter 7 Timing Simulation
Model Technology ModelSim
Verilog
VHDL
Model Technology ModelSim
pcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd
source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd
source/pingtb.vhd
PCI v3.0.151 Getting Started Guide
Chapter 7 Timing Simulation
UG157 August 31