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Xilinx PCI v3.0 12 Create a New Project, 13 Main Project Window, Vhdl, Synthesizing a Design

Models: PCI v3.0

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Chapter 5: Synthesizing a Design

VHDL

1.Start Synplify and choose File > New, or use the new file icon on the toolbar. The New dialog box appears.

Figure 5-12:Create a New Project

2.Under File Type, select Project File and enter the project name (flowtest in this example) and synthesis directory:

<Install Path>/vhdl/example/synthesis

3.Click OK to exit the dialog box and return to the project window.

Figure 5-13:Main Project Window

4.To add source files to the new project, click Add.

The first file (used by any design that instantiates Xilinx primitives) is located in:

<Synplicity Install Path>/lib/xilinx

48	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005

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Xilinx PCI v3.0 manual 12 Create a New Project, 13 Main Project Window, Vhdl, Synthesizing a Design

Contents

UG157 August 31 LogiCORE PCIGetting Started Guide v3.0.151Version RevisionPCI v3.0.151 Getting Started Guide UG157 August 31 Document → PDF Setup VersionRevision PCI v3.0.151 Getting Started Guide UG157 August 31Table of Contents Chapter 2 Installing and Licensing the CorePreface About This Guide Chapter 1 Getting StartedChapter 5 Synthesizing a Design Chapter 6 Implementing a DesignChapter 7 Timing Simulation ISE FoundationGuide Contents About This GuidePreface Additional Resources ConventionsTypographical Preface About This GuideOnline Document ConventionsItalic font lowpwr =onoffPreface About This Guide PCI v3.0.151 Getting Started GuideUG157 August 31 Getting Started ChapterAbout the Example Design Additional DocumentationTechnical Support FeedbackPCI Interface Core DocumentInstalling and Licensing the Core Installing the CoreSystem Requirements ChapterCORE Generator IP Updates Installer Manual Installation CORE Generator IP UpdateChapter 2 Installing and Licensing the Core Installing the Core Direct Download of Standalone CoreLicensing Options EvaluationFull Direct DownloadInstalling Your License File Installing Your License FilePCI v3.0.151 Getting Started Guide UG157 August 31Chapter 2 Installing and Licensing the Core PCI v3.0.151 Getting Started GuideUG157 August 31 Family Specific Considerations Design SupportTable 3-1 Device and Interface Selection Table SupportedChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileWrapper Files Constraints FilesGuide Files Table 3-2 Guide File InformationDevice Initialization Bus Width DetectionDevice Initialization Table 3-2 Guide File Information Figure 3-1 Sample SLOT64 GenerationDatapath Output Clock Enable Input Delay BuffersChapter 3 Family Specific Considerations Input Delay Buffers Table 3-3 Delay Buffer SettingsDelay Setting ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsRegional Clock Usage Table 3-4 Virtex-4 Device and Package 64-bit InterfacesPackage 64-bit InterfacesBus Clock Usage FF668FF672 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceFigure 3-3 Relationship For 3.3V Input Buffer Compliance REGIONSystem Supply 3.3V PCI COMPLIANTGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation Chapter 3 Family Specific Considerations PCI v3.0.151 Getting Started GuideUG157 August 31 Functional Simulation Cadence NC-VerilogChapter Model Technology ModelSim VerilogChapter 4 Functional Simulation VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationSynthesizing a Design Synplicity SynplifyFigure 5-5 Create a New Project ChapterChapter 5 Synthesizing a Design Figure 5-6 Main Project Window Figure 5-7 Select Files to Add LibrarySynplicity Install Path/lib/xilinx Synplicity Synplify Figure 5-8 Files to Add LogiCORE FilesFigure 5-9 Select Files to Add Dialog Box User Application Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source FilesFigure 5-11 Options for Implementation Device Synplicity Synplify16. Click OK to return to the main project window Figure 5-12 Create a New Project Figure 5-13 Main Project WindowVHDL Chapter 5 Synthesizing a DesignFigure 5-14 Select Files to Add Library Figure 5-15 Select Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Xilinx XST Chapter 5 Synthesizing a DesignImplementing a Design ISE FoundationChapter Chapter 6 Implementing a Design Timing Simulation cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.vChapter Cadence NC-VerilogChapter 7 Timing Simulation Model Technology ModelSimVerilog VHDLModel Technology ModelSim pcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhdsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd source/pingtb.vhdChapter 7 Timing Simulation PCI v3.0.151 Getting Started GuideUG157 August 31