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Xilinx PCI v3.0 Family Specific Considerations, 1 Device and Interface Selection Table Continued

Models: PCI v3.0

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Chapter 3: Family Specific Considerations

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Chapter 3: Family Specific Considerations

Table 3-1:Device and Interface Selection Table (Continued)

	Supported	Bus	Wrapper File	Constraints File/
	Device	Type	Wrapper File	Guide File
	Device	Type		Guide File

	2S200-FG456-6C	33 MHz	pcim_lc_33_3_s	2s200fg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S200-FG456-6C	66 MHz	pcim_lc_66_3_d	2s200fg456_64_66.ucf
		3.3V		2s200fg456_64_66.ncd
		64-bit

	2S100E-FG456-6C	33 MHz	pcim_lc_33_3_s	2s100efg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S150E-FG456-6C	33 MHz	pcim_lc_33_3_s	2s150efg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S200E-FG456-6C	33 MHz	pcim_lc_33_3_s	2s200efg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S300E-FG456-6C	33 MHz	pcim_lc_33_3_s	2s300efg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S300E-FG456-6C	66 MHz	pcim_lc_66_3_d	2s300efg456_64_66.ucf
		3.3V		2s300efg456_64_66.ncd
		64-bit

	V100E-BG352-6C	33 MHz	pcim_lc_33_3_s	v100ebg352_64_33.ucf
		3.3V		no guide file
		64-bit

	V300-BG432-6C	66 MHz	pcim_lc_66_3_d	v300bg432_64_66.ucf
		3.3V		v300bg432_64_66.ncd
		64-bit

	V300-BG432-5C	33 MHz	pcim_lc_33_5_s	v300bg432_64_33.ucf
		5.0V		no guide file
		64-bit

	V300-BG432-5C	33 MHz	pcim_lc_33_3_s	v300bg432_64_33.ucf
		3.3V		no guide file
		64-bit

20	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005

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Xilinx PCI v3.0 Family Specific Considerations, 1 Device and Interface Selection Table Continued, Supported, Wrapper File

Contents

UG157 August 31 LogiCORE PCIGetting Started Guide v3.0.151PCI v3.0.151 Getting Started Guide UG157 August 31 VersionRevision Revision Document → PDF SetupVersion PCI v3.0.151 Getting Started Guide UG157 August 31Table of Contents Chapter 2 Installing and Licensing the CorePreface About This Guide Chapter 1 Getting StartedChapter 5 Synthesizing a Design Chapter 6 Implementing a DesignChapter 7 Timing Simulation ISE FoundationPreface Guide ContentsAbout This Guide Additional Resources ConventionsTypographical Preface About This GuideOnline Document ConventionsItalic font lowpwr =onoffUG157 August 31 Preface About This GuidePCI v3.0.151 Getting Started Guide Getting Started ChapterAbout the Example Design Additional DocumentationTechnical Support FeedbackPCI Interface Core DocumentInstalling and Licensing the Core Installing the CoreSystem Requirements ChapterChapter 2 Installing and Licensing the Core CORE Generator IP Updates InstallerManual Installation CORE Generator IP Update Installing the Core Direct Download of Standalone CoreLicensing Options EvaluationFull Direct DownloadInstalling Your License File Installing Your License FilePCI v3.0.151 Getting Started Guide UG157 August 31UG157 August 31 Chapter 2 Installing and Licensing the CorePCI v3.0.151 Getting Started Guide Family Specific Considerations Design SupportTable 3-1 Device and Interface Selection Table SupportedChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileWrapper Files Constraints FilesGuide Files Table 3-2 Guide File InformationDevice Initialization Bus Width DetectionDevice Initialization Table 3-2 Guide File Information Figure 3-1 Sample SLOT64 GenerationChapter 3 Family Specific Considerations Datapath Output Clock EnableInput Delay Buffers Input Delay Buffers Table 3-3 Delay Buffer SettingsDelay Setting ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsRegional Clock Usage Table 3-4 Virtex-4 Device and Package 64-bit InterfacesPackage 64-bit InterfacesBus Clock Usage FF668FF672 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceFigure 3-3 Relationship For 3.3V Input Buffer Compliance REGIONSystem Supply 3.3V PCI COMPLIANTFigure 3-4 Output Driver VCCO Generation Generating BitstreamsGenerating Bitstreams UG157 August 31 Chapter 3 Family Specific ConsiderationsPCI v3.0.151 Getting Started Guide Chapter Functional SimulationCadence NC-Verilog Chapter 4 Functional Simulation Model Technology ModelSimVerilog VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationSynthesizing a Design Synplicity SynplifyFigure 5-5 Create a New Project ChapterSynplicity Install Path/lib/xilinx Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowFigure 5-7 Select Files to Add Library Figure 5-9 Select Files to Add Dialog Box User Application Synplicity SynplifyFigure 5-8 Files to Add LogiCORE Files Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source Files16. Click OK to return to the main project window Figure 5-11 Options for Implementation DeviceSynplicity Synplify Figure 5-12 Create a New Project Figure 5-13 Main Project WindowVHDL Chapter 5 Synthesizing a DesignFigure 5-14 Select Files to Add Library Figure 5-15 Select Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignFigure 5-17 Options for Implementation Exemplar LeonardoSpectrumExemplar LeonardoSpectrum Xilinx XST Chapter 5 Synthesizing a DesignChapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design Timing Simulation cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.vChapter Cadence NC-VerilogChapter 7 Timing Simulation Model Technology ModelSimVerilog VHDLModel Technology ModelSim pcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhdsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd source/pingtb.vhdUG157 August 31 Chapter 7 Timing SimulationPCI v3.0.151 Getting Started Guide