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Xilinx PCI v3.0 Family Specific Considerations, Design Support, Supported, Wrapper File, Device

Models: PCI v3.0

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Family Specific Considerations

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Chapter 3

Family Specific Considerations

This chapter provides important design information specific to the PCI interface targeting Virtex and Spartan devices.

Design Support

Table 3-1provides a list of supported device and interface combinations. Each entry in the table consists of a device, a bus interface type, and two or three specific implementation files.

Table 3-1:Device and Interface Selection Table

	Supported	Bus	Wrapper File	Constraints File/
	Device	Type	Wrapper File	Guide File
	Device	Type		Guide File

	2S100-FG456-6C	33 MHz	pcim_lc_33_5_s	2s100fg456_64_33.ucf
		5.0V		no guide file
		64-bit

	2S100-FG456-6C	33 MHz	pcim_lc_33_3_s	2s100fg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S150-FG456-6C	33 MHz	pcim_lc_33_5_s	2s150fg456_64_33.ucf
		5.0V		no guide file
		64-bit

	2S150-FG456-6C	33 MHz	pcim_lc_33_3_s	2s150fg456_64_33.ucf
		3.3V		no guide file
		64-bit

	2S150-FG456-6C	66 MHz	pcim_lc_66_3_d	2s150fg456_64_66.ucf
		3.3V		2s150fg456_64_66.ncd
		64-bit

	2S200-FG456-6C	33 MHz	pcim_lc_33_5_s	2s200fg456_64_33.ucf
		5.0V		no guide file
		64-bit

PCI v3.0.151 Getting Started Guide

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UG157 August 31, 2005

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Xilinx PCI v3.0 Family Specific Considerations, Design Support, 1 Device and Interface Selection Table, Supported, Chapter

Contents

v3.0.151 UG157 August 31LogiCORE PCI Getting Started GuideRevision VersionPCI v3.0.151 Getting Started Guide UG157 August 31 Version Document → PDF SetupRevision UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 1 Getting Started Table of ContentsChapter 2 Installing and Licensing the Core Preface About This GuideISE Foundation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design Chapter 7 Timing SimulationAbout This Guide Guide ContentsPreface Preface About This Guide Additional ResourcesConventions Typographicallowpwr =onoff Online DocumentConventions Italic fontPCI v3.0.151 Getting Started Guide Preface About This GuideUG157 August 31 Additional Documentation Getting StartedChapter About the Example DesignDocument Technical SupportFeedback PCI Interface CoreChapter Installing and Licensing the CoreInstalling the Core System RequirementsManual Installation CORE Generator IP Update CORE Generator IP Updates InstallerChapter 2 Installing and Licensing the Core Direct Download of Standalone Core Installing the CoreDirect Download Licensing OptionsEvaluation FullUG157 August 31 Installing Your License FileInstalling Your License File PCI v3.0.151 Getting Started GuidePCI v3.0.151 Getting Started Guide Chapter 2 Installing and Licensing the CoreUG157 August 31 Supported Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface Selection TableWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedTable 3-2 Guide File Information Wrapper FilesConstraints Files Guide FilesFigure 3-1 Sample SLOT64 Generation Device InitializationBus Width Detection Device Initialization Table 3-2 Guide File InformationInput Delay Buffers Datapath Output Clock EnableChapter 3 Family Specific Considerations Implementation Input Delay BuffersTable 3-3 Delay Buffer Settings Delay SettingChapter 3 Family Specific Considerations Regional Clock Usage64-bit Interfaces Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces PackageChapter 3 Family Specific Considerations Bus Clock UsageFF668 FF672Electrical Compliance Electrical Compliance3.3V PCI COMPLIANT Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION System SupplyGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation PCI v3.0.151 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG157 August 31 Cadence NC-Verilog Functional SimulationChapter Verilog Model Technology ModelSimChapter 4 Functional Simulation Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimChapter Synthesizing a DesignSynplicity Synplify Figure 5-5 Create a New ProjectFigure 5-7 Select Files to Add Library Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowSynplicity Install Path/lib/xilinx Figure 5-8 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-9 Select Files to Add Dialog Box User Application Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a DesignSynplicity Synplify Figure 5-11 Options for Implementation Device16. Click OK to return to the main project window Chapter 5 Synthesizing a Design Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window VHDLSynplicity Synplify Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Install Path/vhdl/src/xpciChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Chapter 5 Synthesizing a Design Xilinx XSTISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Cadence NC-Verilog Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v ChapterVHDL Chapter 7 Timing SimulationModel Technology ModelSim Verilogsource/pingtb.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhdPCI v3.0.151 Getting Started Guide Chapter 7 Timing SimulationUG157 August 31