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PCI v3.0 manual UG157 August 31, LogiCORE PCI, Getting Started Guide, v3.0.151
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LogiCORE™ PCI v3.0
Getting Started Guide
UG157 August 31, 2005
v3.0.151
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Contents
LogiCORE PCI
UG157 August 31
Getting Started Guide
v3.0.151
Revision
Version
PCI v3.0.151 Getting Started Guide UG157 August 31
Version
Document → PDF Setup
Revision
UG157 August 31
PCI v3.0.151 Getting Started Guide
Chapter 2 Installing and Licensing the Core
Table of Contents
Preface About This Guide
Chapter 1 Getting Started
Chapter 6 Implementing a Design
Chapter 5 Synthesizing a Design
Chapter 7 Timing Simulation
ISE Foundation
About This Guide
Guide Contents
Preface
Conventions
Additional Resources
Typographical
Preface About This Guide
Conventions
Online Document
Italic font
lowpwr =onoff
PCI v3.0.151 Getting Started Guide
Preface About This Guide
UG157 August 31
Chapter
Getting Started
About the Example Design
Additional Documentation
Feedback
Technical Support
PCI Interface Core
Document
Installing the Core
Installing and Licensing the Core
System Requirements
Chapter
Manual Installation CORE Generator IP Update
CORE Generator IP Updates Installer
Chapter 2 Installing and Licensing the Core
Direct Download of Standalone Core
Installing the Core
Evaluation
Licensing Options
Full
Direct Download
Installing Your License File
Installing Your License File
PCI v3.0.151 Getting Started Guide
UG157 August 31
PCI v3.0.151 Getting Started Guide
Chapter 2 Installing and Licensing the Core
UG157 August 31
Design Support
Family Specific Considerations
Table 3-1 Device and Interface Selection Table
Supported
Table 3-1 Device and Interface Selection Table Continued
Chapter 3 Family Specific Considerations
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Design Support
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Chapter 3 Family Specific Considerations
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Design Support
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Chapter 3 Family Specific Considerations
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Design Support
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Chapter 3 Family Specific Considerations
Supported
Wrapper File
Table 3-1 Device and Interface Selection Table Continued
Design Support
Supported
Wrapper File
Constraints Files
Wrapper Files
Guide Files
Table 3-2 Guide File Information
Bus Width Detection
Device Initialization
Device Initialization Table 3-2 Guide File Information
Figure 3-1 Sample SLOT64 Generation
Input Delay Buffers
Datapath Output Clock Enable
Chapter 3 Family Specific Considerations
Table 3-3 Delay Buffer Settings
Input Delay Buffers
Delay Setting
Implementation
Chapter 3 Family Specific Considerations
Regional Clock Usage
Table 3-4 Virtex-4 Device and Package 64-bit Interfaces
Regional Clock Usage
Package
64-bit Interfaces
FF668
Bus Clock Usage
FF672
Chapter 3 Family Specific Considerations
Electrical Compliance
Electrical Compliance
REGION
Figure 3-3 Relationship For 3.3V Input Buffer Compliance
System Supply
3.3V PCI COMPLIANT
Generating Bitstreams
Generating Bitstreams
Figure 3-4 Output Driver VCCO Generation
PCI v3.0.151 Getting Started Guide
Chapter 3 Family Specific Considerations
UG157 August 31
Cadence NC-Verilog
Functional Simulation
Chapter
Verilog
Model Technology ModelSim
Chapter 4 Functional Simulation
Model Technology ModelSim
VHDL
Chapter 4 Functional Simulation
Install Path/vhdl/example/funcsim
Synplicity Synplify
Synthesizing a Design
Figure 5-5 Create a New Project
Chapter
Figure 5-7 Select Files to Add Library
Chapter 5 Synthesizing a Design Figure 5-6 Main Project Window
Synplicity Install Path/lib/xilinx
Figure 5-8 Files to Add LogiCORE Files
Synplicity Synplify
Figure 5-9 Select Files to Add Dialog Box User Application
Figure 5-10 Main Project Window with Source Files
Chapter 5 Synthesizing a Design
Synplicity Synplify
Figure 5-11 Options for Implementation Device
16. Click OK to return to the main project window
Figure 5-13 Main Project Window
Figure 5-12 Create a New Project
VHDL
Chapter 5 Synthesizing a Design
Figure 5-15 Select Files to Add LogiCORE Files
Figure 5-14 Select Files to Add Library
Install Path/vhdl/src/xpci
Synplicity Synplify
Chapter 5 Synthesizing a Design
Figure 5-16 Project Window with Source Files
Exemplar LeonardoSpectrum
Exemplar LeonardoSpectrum
Figure 5-17 Options for Implementation
Chapter 5 Synthesizing a Design
Xilinx XST
ISE Foundation
Implementing a Design
Chapter
Chapter 6 Implementing a Design
cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v
Timing Simulation
Chapter
Cadence NC-Verilog
Model Technology ModelSim
Chapter 7 Timing Simulation
Verilog
VHDL
pcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd
Model Technology ModelSim
source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd
source/pingtb.vhd
PCI v3.0.151 Getting Started Guide
Chapter 7 Timing Simulation
UG157 August 31