Generating Bitstreams

R

Figure 3-4shows one possible low-cost solution to generate the required 3.0 volt output driver supply. Xilinx recommends the use of the circuit shown in Figure 3-4, although other approaches using other regulators are possible.

SUPPLY

8

 

5

7

6

1.0 uF

GND

INOUT

SHDN# ADJ

GNDBYP

GNDGND

LT1763CS8 +3.0V SUPPLY

1

VCCO

2

4

3

38.3, 1%

3.3 uF

26.1, 1%

Figure 3-4:Output Driver VCCO Generation

Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E devices, as specified in the relevant device data sheets, exhibit a 10 pF pin capacitance. This is compliant with the PCI Local Bus Specification, with one exception. The specification requires an 8 pF pin capacitance for the IDSEL pin, to allow for non-resistive coupling to an AD[xx] pin. In practice, this coupling may be resistive or non-resistive, and is performed on the system board or backplane. For system board or backplane designs, use resistive coupling to avoid non-compliance. For add-in cards, this is not under the control of the designer.

Although the PCI interface does not directly provide the PME# signal for power management event reporting, it may be implemented by the user application. A typical implementation would involve the implementation of the power management capability item in user configuration space, along with a dedicated PME# output on a general purpose I/O pin.

On all device families, if the FPGA power is removed, the general purpose I/O pin will appear as a low impedance to ground. This appears to the system as an assertion of PME#. For this reason, implementations that use the PME# signal should employ an external buffering scheme that will prevent false assertions of PME# when power is removed from the FPGA device.

Generating Bitstreams

The bitstream generation program, bitgen, may issue DRC warnings when generating bitstreams for PCI designs. The number of these warnings varies depending on the configuration options used for the PCI core. Typically, these warnings are related to nets with no loads generated during trimming by the map program. Some of these nets are intentionally preserved by statements in the user constraints file.

For some 66 MHz designs, bitgen must be run with a special option to change the behavior of a global clock buffer used in the design:

bitgen -g Gclkdel<buf>:<opt> pcim_top_routed.ncd

See the release notes and the user constraints file for additional information about the use and implications of this required option.

PCI v3.0.151 Getting Started Guide

www.xilinx.com

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UG157 August 31, 2005

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Xilinx PCI v3.0 manual Generating Bitstreams
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PCI v3.0 specifications

Xilinx PCI Express (PCIe) v3.0 technology represents a significant leap in performance and efficiency for high-speed data transfer applications. As a critical interface standard for connecting peripheral devices to a host system, PCIe v3.0 introduces numerous enhancements that ensure faster data rates, increased bandwidth, and lower latency, meeting the rigorous demands of modern computing environments.

One of the standout features of PCIe v3.0 is its increased data transfer rate, which doubles the bandwidth compared to its predecessor, PCIe v2.0. This version supports a maximum theoretical bandwidth of 8 GT/s (gigatransfers per second) per lane, leading to an aggregate bandwidth of up to 32 GB/s with four lanes operating simultaneously, which is crucial for applications in data-intensive fields such as telecommunications, data centers, and high-performance computing.

Xilinx’s PCIe v3.0 solutions incorporate advanced error-handling mechanisms and improved power management. The technology employs a robust 128/130b encoding scheme that minimizes overhead while ensuring data integrity. Additionally, PCIe v3.0 supports native high-speed signaling, which not only reduces power consumption but also enhances signal quality, leading to greater reliability in data transmission.

The flexibility of Xilinx’s PCIe v3.0 implementation makes it ideal for various applications, including artificial intelligence, machine learning, and video processing, where rapid data throughput is paramount. Moreover, Xilinx provides extensive support through its Vivado Design Suite, enabling developers to easily integrate PCIe functionality into their designs while optimizing performance for specific applications through customizable settings.

Another key characteristic is the backward compatibility with earlier PCIe versions. This ensures that existing hardware can leverage new capabilities without necessitating a complete overhaul of the infrastructure, enhancing investment protection for users. The inclusion of additional features such as enhanced message signaling and the ability to support up to 64 thousand in-flight transactions further boosts the efficiency of data handling in a multi-threaded environment.

In summary, Xilinx PCI Express v3.0 technology is a powerful solution that combines high bandwidth, reduced latency, and enhanced reliability, making it an essential component for advanced computing architectures. Its robust features, coupled with Xilinx’s design tools and support, provide developers with the resources needed to push the boundaries of data transfer capabilities in a growing range of applications.
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