Manuals / Xilinx / Computer Equipment / Switch

Xilinx PCI v3.0 manual Document → PDF Setup, Version, Revision

Models: PCI v3.0

1 58

Download 58 pages 41.49 Kb

Page 3

Document → PDF Setup...

	Version	Revision

06/24/02	3.0	Initial Xilinx release of corporate-wide common template set, used for User Guides,
		Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents
		created by both CMP and ITP. See related documents for further information.
		Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision
		changes prior to v3.0, refer to v2.2.1 template set.

10/30/02	3.1	Updated spelling of RocketIO and SelectIO trademarks in ug000_title.fm per 10/09/02
		broadcast email announcement. Also updated file version number and date.

12/06/02	3.2	Fixed all instances of old character formats in header/footer in Master pages.

01/20/03	3.3	Revised copyright date in ug000_title.fm to 2003. Changed all instances of “Manual” in
		ug000_preface.fm to “Guide”. Added PDF Information format under Format →
		Document → PDF Setup...

02/06/03	3.4	Added paragraph formats GlossBulleted, GlossNumbered, and GlossNumberedCont.

02/25/03	3.4.1	Minor clean-ups and corrections.

03/25/03	3.5	• Corrected Reference Page identification problem that prevented the IX (index)
		Reference page from taking control of Index formatting.
		• Modified paragraph tags Level1IX through Level3IX (index entries) to provide a
		more uniform appearance and enhance clarity.
		• Removed <Italic> attribute from Heading2TOC special string on Reference pages.
		• Changed autonumbering properties of FigureTitle and TableTitle to remove chapter
		number and hyphen.

04/30/03	3.5.1	Updated Additional Resources table in Preface to give correct URL to data sheets index
		page instead of to obsolete Programmable Logic Data Book page.

11/11/04	3.5.2	Added installation and licensing chapter; updated to current template.

12/01/04	3.6	Updated to include Virtex-4 information.

3/7/05	3.7	Updated to ISE 7.1i and build number 3.0.145.

5/13/05	4.0	Updated to build 3.0.150 and Xilinx tools 7.1i SP2.

8/31/05	5.0	Updated to build 3.0.151 and Xilinx tools 7.1i SP4.

www.xilinx.com	PCI v3.0.151 Getting Started Guide
	UG157 August 31, 2005

Image 3

Xilinx PCI v3.0 manual Document → PDF Setup, Version, Revision

Contents

v3.0.151 UG157 August 31LogiCORE PCI Getting Started GuideVersion RevisionPCI v3.0.151 Getting Started Guide UG157 August 31 Document → PDF Setup VersionRevision UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 1 Getting Started Table of ContentsChapter 2 Installing and Licensing the Core Preface About This GuideISE Foundation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design Chapter 7 Timing SimulationGuide Contents About This GuidePreface Preface About This Guide Additional ResourcesConventions Typographicallowpwr =onoff Online DocumentConventions Italic fontPreface About This Guide PCI v3.0.151 Getting Started GuideUG157 August 31 Additional Documentation Getting StartedChapter About the Example DesignDocument Technical SupportFeedback PCI Interface CoreChapter Installing and Licensing the CoreInstalling the Core System RequirementsCORE Generator IP Updates Installer Manual Installation CORE Generator IP UpdateChapter 2 Installing and Licensing the Core Direct Download of Standalone Core Installing the CoreDirect Download Licensing OptionsEvaluation FullUG157 August 31 Installing Your License FileInstalling Your License File PCI v3.0.151 Getting Started GuideChapter 2 Installing and Licensing the Core PCI v3.0.151 Getting Started GuideUG157 August 31 Supported Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface Selection TableWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedTable 3-2 Guide File Information Wrapper FilesConstraints Files Guide FilesFigure 3-1 Sample SLOT64 Generation Device InitializationBus Width Detection Device Initialization Table 3-2 Guide File InformationDatapath Output Clock Enable Input Delay BuffersChapter 3 Family Specific Considerations Implementation Input Delay BuffersTable 3-3 Delay Buffer Settings Delay SettingChapter 3 Family Specific Considerations Regional Clock Usage64-bit Interfaces Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces PackageChapter 3 Family Specific Considerations Bus Clock UsageFF668 FF672Electrical Compliance Electrical Compliance3.3V PCI COMPLIANT Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION System SupplyGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation Chapter 3 Family Specific Considerations PCI v3.0.151 Getting Started GuideUG157 August 31 Functional Simulation Cadence NC-VerilogChapter Model Technology ModelSim VerilogChapter 4 Functional Simulation Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimChapter Synthesizing a DesignSynplicity Synplify Figure 5-5 Create a New ProjectChapter 5 Synthesizing a Design Figure 5-6 Main Project Window Figure 5-7 Select Files to Add LibrarySynplicity Install Path/lib/xilinx Synplicity Synplify Figure 5-8 Files to Add LogiCORE FilesFigure 5-9 Select Files to Add Dialog Box User Application Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a DesignFigure 5-11 Options for Implementation Device Synplicity Synplify16. Click OK to return to the main project window Chapter 5 Synthesizing a Design Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window VHDLSynplicity Synplify Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Install Path/vhdl/src/xpciChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Chapter 5 Synthesizing a Design Xilinx XSTImplementing a Design ISE FoundationChapter Chapter 6 Implementing a Design Cadence NC-Verilog Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v ChapterVHDL Chapter 7 Timing SimulationModel Technology ModelSim Verilogsource/pingtb.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhdChapter 7 Timing Simulation PCI v3.0.151 Getting Started GuideUG157 August 31