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Xilinx PCI v3.0 manual Implementing a Design

Models: PCI v3.0

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Chapter 6: Implementing a Design

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Chapter 6: Implementing a Design

•The par command, as provided in the script, uses a guide file in exact guide mode. Note that some designs do not require the use of guide files.

To target a different device or to use a different version of the PCI interface, see Chapter 3, “Family Specific Considerations.”

If a guide file is required, ensure that the correct guide file is used by editing the script and changing the file name. If a guide file is not required, remove the following input arguments from the par command line in the script:

-gm exact -gf ../../src/guide/guidefile.ncd

If a guide file is required, the guide file must always be used. The effort levels and delay cleanup iterations may be adjusted if necessary.

•The trce command performs a static timing analysis based on the design constraints originally specified in the user constraints file.

•The netgen command generates a simulation model of the placed and routed design.

3.Implement the design by running the appropriate script.

During initial processing trials, it is useful to enter commands one at a time from the command line rather than running the script so that you can inspect the output of each step.

If the use of a guide file is required, it is important to verify that the guiding process was successful. This may be done by inspecting the pcim_top_routed.grf file. The remainder of this section is specific to designs requiring the use of guide files.

The number of pre-routed connections should exactly match the number listed in the selection table, shown in Table 3-1, page 19. The number of unrouted signals varies depending on the size of the user application. If the number does not match, the guide process has failed. This can occur for several reasons. First, check that the correct user constraints and guide files have been used. Second, verify that the user application observes all signal-driving rules defined in the PCI User Guide.

Note: Do not attempt re-entrant routing on a guided design. Re-entrant routing must not be used as it may re-route nets that were initially guided by the guide file.

54	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005

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Xilinx PCI v3.0 manual Implementing a Design

Contents

Getting Started Guide UG157 August 31LogiCORE PCI v3.0.151Version RevisionPCI v3.0.151 Getting Started Guide UG157 August 31 Document → PDF Setup VersionRevision PCI v3.0.151 Getting Started Guide UG157 August 31Preface About This Guide Table of ContentsChapter 2 Installing and Licensing the Core Chapter 1 Getting StartedChapter 7 Timing Simulation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design ISE FoundationGuide Contents About This GuidePreface Typographical Additional ResourcesConventions Preface About This GuideItalic font Online DocumentConventions lowpwr =onoffPreface About This Guide PCI v3.0.151 Getting Started GuideUG157 August 31 About the Example Design Getting StartedChapter Additional DocumentationPCI Interface Core Technical SupportFeedback DocumentSystem Requirements Installing and Licensing the CoreInstalling the Core ChapterCORE Generator IP Updates Installer Manual Installation CORE Generator IP UpdateChapter 2 Installing and Licensing the Core Installing the Core Direct Download of Standalone CoreFull Licensing OptionsEvaluation Direct DownloadPCI v3.0.151 Getting Started Guide Installing Your License FileInstalling Your License File UG157 August 31Chapter 2 Installing and Licensing the Core PCI v3.0.151 Getting Started GuideUG157 August 31 Table 3-1 Device and Interface Selection Table Family Specific ConsiderationsDesign Support SupportedSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileGuide Files Wrapper FilesConstraints Files Table 3-2 Guide File InformationDevice Initialization Table 3-2 Guide File Information Device InitializationBus Width Detection Figure 3-1 Sample SLOT64 GenerationDatapath Output Clock Enable Input Delay BuffersChapter 3 Family Specific Considerations Delay Setting Input Delay BuffersTable 3-3 Delay Buffer Settings ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsPackage Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces 64-bit InterfacesFF672 Bus Clock UsageFF668 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceSystem Supply Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION 3.3V PCI COMPLIANTGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation Chapter 3 Family Specific Considerations PCI v3.0.151 Getting Started GuideUG157 August 31 Functional Simulation Cadence NC-VerilogChapter Model Technology ModelSim VerilogChapter 4 Functional Simulation VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationFigure 5-5 Create a New Project Synthesizing a DesignSynplicity Synplify ChapterChapter 5 Synthesizing a Design Figure 5-6 Main Project Window Figure 5-7 Select Files to Add LibrarySynplicity Install Path/lib/xilinx Synplicity Synplify Figure 5-8 Files to Add LogiCORE FilesFigure 5-9 Select Files to Add Dialog Box User Application Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source FilesFigure 5-11 Options for Implementation Device Synplicity Synplify16. Click OK to return to the main project window VHDL Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window Chapter 5 Synthesizing a DesignInstall Path/vhdl/src/xpci Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Xilinx XST Chapter 5 Synthesizing a DesignImplementing a Design ISE FoundationChapter Chapter 6 Implementing a Design Chapter Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v Cadence NC-VerilogVerilog Chapter 7 Timing SimulationModel Technology ModelSim VHDLsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/pingtb.vhdChapter 7 Timing Simulation PCI v3.0.151 Getting Started GuideUG157 August 31