Intel MultiProcessor manual Hardware Specification, System Memory Configuration

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3 Hardware Specification

This section outlines the minimal set of common hardware features necessary for the operating system to operate on multiple hardware platforms. The MP hardware specification defines how the components mentioned in Chapter 2 are implemented. Compliance to the specification involves the following aspects of hardware implementation:

System memory configuration

System memory cacheability and shareability

External cache implementation requirements

Control of memory contention (locking)

Ordering of posted memory writes

Multiprocessor interrupt control

Reset support

Interval timer usage

Support for fault-resilient booting

While the bulk of the MP hardware specification pertains to multiprocessor interrupt control, other areas also require some attention. The following sections take up each of these topics in turn.

3.1 System Memory Configuration

The MP memory specifications are based on the standard PC/AT memory map, which currently has a physical memory space of four gigabytes, as shown in see Figure 3-1. Physical memory should begin at 0 and be contiguous. Memory-mapped I/O devices should be mapped at the top of physical memory. The APIC default base memory addresses defined by this specification are 0FEC0_0000h and 0FEE0_0000h.

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsFeatures of the Specification MultiProcessor SpecificationScope Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number