Intel MultiProcessor manual PIC Mode

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MultiProcessor Specification

		BSP		AP1		AP2
IMCR		CPU 1		CPU 2		CPU 3
IMCR
E0	NMI	INTR		NMI INTR		NMI INTR
		LOCAL		LOCAL		LOCAL
REG.		APIC		APIC		APIC
REG.			1	2			3
MARK	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0	LINTIN1
	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0	LINTIN1
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
				8259A-	INTR
				EQUIVALENT
				PICS
INTERRUPT INPUTS							I/O
INTERRUPT INPUTS						APIC

SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.

Figure 3-2. PIC Mode

The IMCR is supported by two read/writable or write-only I/O ports, 22h and 23h, which receive address and data respectively. To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR. Then write the data to I/O port 23h. The power-on default value is zero, which connects the NMI and 8259 INTR lines directly to the BSP. Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.

The IMCR must be cleared after a system-wide INIT or RESET to enable the PIC Mode as default. (Refer to Section 3.7 for information on the INIT and RESET signals.)

The IMCR is optional if PIC Mode is not implemented. The IMCRP bit of the MP feature information bytes (refer to Chapter 4) enables the operating system to detect whether the IMCR is implemented.

3-8	Version 1.4

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewMultiProcessor Specification Features of the SpecificationScope Target Audience Organization of This DocumentDocument Organization IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingMultiprocessor Interrupt Control Posted Memory WriteApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeFloating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description MP Feature Offset Length Field Bytesbits Bits DescriptionInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderMP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Base MP Configuration Table Entry Types Processor EntriesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Feature Flags from Cpuid Instruction Intel486 and Pentium Processor SignaturesFamily Model Stepping a Description Bit Name Description CommentsBus Entries BUS IDBUS Type StringBus Type String Values Bus Type String Description3 I/O Apic Entries 4 I/O Interrupt Assignment EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments 12. Local Interrupt Entry Fields Destination Local Apic IDDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Discrete Apic Configurations Default ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Default Configuration Interrupt Assignments Config INTINx CommentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAll Local APICs Config LINTINx Comments Assignment of System Interrupts to the Apic Local UnitEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingOther IPI Applications Spurious Apic InterruptsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Bus Entries in Systems with More Than One PCI Bus I/O Interrupt Assignment Entries for PCI DevicesMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry14. System Address Space Mapping Entry Fields Entry LengthAddress Type Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number