Intel MultiProcessor manual System Overview

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2 System Overview

In the realm of multiprocessor architectures, there are several conceptual models for tying together computing elements, and there are a variety of interconnection schemes and details of implementation. Figure 2-1 shows the general structure of a design based on the MP specification. The MP specification’s model of multiprocessor systems incorporates a tightly-coupled, shared- memory architecture with a distributed interprocessor and I/O interrupt capability. It is fully symmetric; that is, all processors are functionally identical and of equal status, and each processor can communicate with every other processor. There is no hierarchy, no master-slave relationship, no geometry that limits communication only to “neighboring” processors. The model is symmetric in two important respects:

∙Memory symmetry. Memory is symmetric when all processors share the same memory space and access that space by the same addresses. Memory symmetry offers a very important feature—the ability for all processors to execute a single copy of the operating system. Any existing system and application software will execute the same, regardless of the number of processors installed in a system.

∙I/O symmetry. I/O is symmetric when all processors share access to the same I/O subsystem (including I/O ports and interrupt controllers) and any processor can receive interrupts from any source. Some multiprocessor systems that have symmetric access to memory are actually asymmetric with regard to I/O interrupts, because they dedicate one processor to interrupt functions. I/O symmetry helps eliminate the potential of an I/O bottleneck, thereby increasing system scalability.

With both memory and I/O symmetry, a system that complies with the MP specification can achieve hardware scalability as well as support software standardization. Based on this kind of scalable architecture, systems developers can produce systems that span a wide range of price and performance, and that all execute the same binaries.

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsFeatures of the Specification MultiProcessor SpecificationScope Introduction Target AudienceOrganization of This Document Document OrganizationFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information ByteMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes CommentsProcessor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a DescriptionString Bus EntriesBUS ID BUS TypeBus Type String Description Bus Type String ValuesI/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic EntryI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local ApicExtended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number BusDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O UnitLevel-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13MultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPIHandling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache FlushSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping EntriesAddress Base 14. System Address Space Mapping Entry FieldsEntry Length Address TypeSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number