Intel MultiProcessor Intel486 and Pentium Processor Signatures, Bit Name Description Comments

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MP Configuration Table

Table 4-5. Intel486 and Pentium Processor Signatures

Family

Model

Steppinga

Description

 

 

 

 

0000

0000

0000

Not a valid CPU signature.

 

 

 

 

0100

0000 and 0001

xxxx

Intel486 DX Processor

 

 

 

 

0100

0010

xxxx

Intel486 SX Processor

 

 

 

 

0100

0011

xxxx

Intel487 Processor

 

 

 

 

0100

0011

xxxx

IntelDX2™ Processor

 

 

 

 

0100

0100

xxxx

Intel486 SL Processor

 

 

 

 

0100

0101

xxxx

IntelSX2™ Processor

 

 

 

 

0100

1000

xxxx

IntelDX4™ Processor

 

 

 

 

0101

0001

xxxx

Pentium Processors (510\60, 567\66)

 

 

 

 

0101

0010

xxxx

Pentium Processors (735\90, 815\100)

 

 

 

Values not shown are reserved for future processors.

 

Refer to the documentation of each new processor for its family and model values.

 

 

 

 

1111

1111

1111

Not a valid CPU signature. Indicates a processor that is not

 

 

 

an Intel architecture-compatible processor (a graphics

 

 

 

controller, for example)

a Intel releases information about stepping numbers as needed.

Table 4-6. Feature Flags from CPUID Instruction

Bit

Name

Description

Comments

0

FPU

On-chip Floating

The processor contains an FPU that supports the Intel387

 

 

Point Unit

processor floating point instruction set.

 

 

 

 

1–6

 

 

Reserved.

 

 

 

 

7

MCE

Machine Check

Exception 18 is defined for machine checks, including CR4.MCE for

 

 

Exception

controlling the feature. This feature does not define the model-

 

 

 

specific implementations of machine-check error logging reporting

 

 

 

and processor shutdowns. Machine-check exception handlers may

 

 

 

have to depend on processor version to do model-specific

 

 

 

processing of the exception or test for the presence of the standard

 

 

 

machine-check feature.

 

 

 

 

8

CX8

CMPXCHG8B

The 8 byte (64 bits) compare-and-exchange instruction is supported

 

 

Instruction

(implicitly locked and atomic). Introduced by the Pentium

 

 

 

processor.

 

 

 

 

9

APIC

On-chip APIC

Indicates that an integrated APIC is present and hardware enabled.

 

 

 

(Software disabling does not affect this bit.)

 

 

 

 

10–31

 

 

Reserved.

 

 

 

 

Version 1.4

4-9

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsFeatures of the Specification MultiProcessor SpecificationScope Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number