Intel MultiProcessor manual Default Configuration for Integrated Apic

Page 65

Default Configurations

 

BSP

 

AP

 

 

PENTIIUM (735\90, 815\100)

 

PENTIUM (735\90, 815\100)

 

CPU1

 

CPU2

APICEN

LOCAL

APICEN

LOCAL

 

APIC

 

APIC

REG.

 

 

 

 

MARK

 

 

 

 

 

 

INTR/LINT0

 

 

NMI

 

NMI/LINT1

 

 

INIT

 

INIT

 

 

SMI#

 

SMI#

 

 

 

ICC BUS

 

 

 

IRQ1

 

 

0

 

 

 

 

1

 

A

 

3

2

 

 

3

 

 

4

 

8254 TIMER

 

4

 

 

5

 

 

 

5

 

 

 

6

 

 

 

6

I/O

 

 

7

IRQ8#

INT8

7

 

APIC

 

 

9

8

 

 

9

 

 

 

10

 

 

 

10

 

 

 

11

 

 

 

11

 

IRQ13

 

 

 

 

13

12

 

 

 

13

 

B

 

14

 

 

14

 

 

15

 

 

15

 

EISA DMA CHAINING

 

 

 

 

 

FROM BSP

 

 

 

 

 

 

FERR#

FERR

 

 

 

0

 

IGNNE#

 

 

 

 

SAMPLING

 

 

 

 

 

 

 

1

 

 

 

 

3

 

2

MASTER INTR

 

 

 

 

3

 

 

 

4

 

4

8259A PIC

 

 

 

5

 

 

 

 

 

5

 

 

 

 

6

 

 

ABFULL

ABFULL

 

 

6

 

 

7

 

 

 

 

7

 

(PS/2 MOUSE)

SAMPLING

 

12

 

 

 

 

 

 

 

 

PIRQ0-3

 

 

 

 

 

 

C

 

 

 

0

 

 

EDGE/LEVEL TRIGGER

 

9

1

 

 

POLARITY CONTROL

 

10

2

 

 

 

11

SLAVE

 

D

 

3

IRQ3-7,

 

12

IRQx

 

 

4

8259A PIC

9-12,14,15

PIRQ

 

5

 

 

LITMx

14

 

IMCR

 

6

 

LITM3-7,

 

MAPPING

15

 

 

7

 

 

 

3-7,9-11,14,15

 

E0

9-12,14,15

 

 

 

 

 

 

 

 

 

 

SHADED AREAS:

A,B: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS

B,C: EISA BUS SPECIFIC

D: PCI BUS SPECIFIC

Figure 5-2. Default Configuration for Integrated APIC

Two local interrupt input pins, LINT0 and LINT1, are shared with the INTR and NMI pins, respectively. The LINT0, LINT1, SMI# and INIT signals are switched by APICEN, and they

Version 1.4

5-5

Page 64 Page 66
Image 65
Page 64 Page 66
Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables FiguresExamples Page Conceptual Overview GoalsScope Features of the SpecificationMultiProcessor Specification Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemApic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeApic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderOffset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number
Top Page Image Contents