
| 
 | 
 | 
 | Table of Contents | |
| Chapter 1 Introduction | 
 | 
 | ||
| 1.1 | Goals | 
 | ||
| 1.2 | Features of the Specification | |||
| 1.3 | Scope | 
 | ||
| 1.4 | Target Audience | ....................................................................................... | ||
| 1.5 | Organization of This Document | |||
| 1.6 | Conventions Used in This Document | |||
| 1.7 | For More Information | |||
| Chapter 2 System Overview | 
 | |||
| 2.1 | Hardware Overview | |||
| 
 | 2.1.1 | System Processors | ||
| 
 | 2.1.2 Advanced Programmable Interrupt Controller | |||
| 
 | 2.1.3 | System Memory | ||
| 
 | 2.1.4 | I/O Expansion Bus | ||
| 2.2 | BIOS Overview | |||
| 2.3 | Operating System Overview | |||
| Chapter 3 Hardware Specification | 
 | |||
| 3.1 | System Memory Configuration | |||
| 3.2 | System Memory Cacheability and Shareability | |||
| 3.3 | External Cache Subsystem | |||
| 3.4 | Locking | ..................................................................................................... | ||
| 3.5 | Posted Memory Write | |||
| 3.6 | Multiprocessor Interrupt Control | |||
| 
 | 3.6.1 | APIC Architecture | ||
| 
 | 3.6.2 | Interrupt Modes | ||
| 
 | 
 | 3.6.2.1 | PIC Mode | |
| 
 | 
 | 3.6.2.2 | Virtual Wire Mode | |
| 
 | 
 | 3.6.2.3 | Symmetric I/O Mode | |
| 
 | 3.6.3 Assignment of System Interrupts to the APIC Local Unit | |||
| 
 | 3.6.4 Floating Point Exception Interrupt | |||
| 
 | 3.6.5 | APIC Memory Mapping | ||
v