Intel MultiProcessor manual Glossary-2

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MultiProcessor Specification

PIC Mode: One of three interrupt modes defined by the MP specification. In this mode the APICs are effectively disabled, while interrupts are generated by 8259A-equivalent PICs and delivered directly to the BSP. This is a uniprocessor compatibility mode.

POST: Power-On Self Test, the first BIOS procedure executed after a RESET or INIT.

RESET: The system-wide hard reset. This definition is functional. It may refer to the RESET signal on both Pentium and Intel486 processors or the RESET signal of the 82489DX APIC.

Shutdown code: The value of CMOS RAM location 0Fh, which indicates that reason that a RESET was performed.

STARTUP IPI: A type of APIC interprocessor interrupt that is similar to an NMI with an embedded vector. It does not cause any change of state, but merely causes the targeted processor to start executing in Real Mode from address 000VV000h, VV being an 8-bit vector which is part of the IPI message. Startup vectors are limited to a 4K page boundary in the first 1 MB of the address space. STARTUP IPIs are not maskable, and can be issued at any time. The benefit of STARTUP-IPI compared to NMI is that it does not require the targeted APIC to be enabled, and it does not require the interrupt table to be programmed. Thus, the operating system's initialization procedure can use it to wake up an AP that has been sleeping since RESET or INIT. The STARTUP IPI is not supported by the 82489DX APIC.

Symmetric I/O Mode: One of three interrupt modes defined by the MP specification. In this mode, the APICs are fully functional, and interrupts are generated and delivered to the processors by the APICs. Any interrupt can be delivered to any processor. This is the only multiprocessor interrupt mode.

Symmetry: The relationship of equality among components of a multiprocessor system in which no processor is special with respect to its access to memory, interrupts, or I/O. For interrupts, symmetry means that any interrupt from any source can be routed to any processor and handled there. For I/O, it means that all I/O control registers, be they in memory space, I/O space, or some other special address space, are accessible to all processors. Per-processor control hardware, such as interrupt controllers or processor identification registers, must be at the same physical address for all processors.

Virtual Wire Mode: One of three interrupt modes defined by the MP specification. In this mode interrupts are generated by the 8259A-equivalent PICs, but delivered to the BSP by an APIC that is programmed to act as a "virtual wire"; that is, the APIC is logically indistinguishable from a hardwired connection. This is a uniprocessor compatibility mode.

Warm reset: A technique that allows the RESET or INIT signal to be asserted without actually causing the BIOS to run through its entire initialization procedure. If a value of 0Ah is placed in the shutdown code, the first instructions of the BIOS POST procedure read the warm-reset vector from system RAM location 40:67h, and jump to that address.

Write-back:A cache update policy wherein a modified cache line is not written back to main memory until the last possible instant—when another processor needs to access the data or when its location in the cache is needed for other data.

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewFeatures of the Specification MultiProcessor SpecificationScope Target Audience Organization of This DocumentDocument Organization IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description MP Feature Offset Length Field Bytesbits Bits DescriptionInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Base MP Configuration Table Entry Types Processor EntriesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Feature Flags from Cpuid Instruction Intel486 and Pentium Processor SignaturesFamily Model Stepping a Description Bit Name Description CommentsBus Entries BUS IDBUS Type StringBus Type String Values Bus Type String Description3 I/O Apic Entries 4 I/O Interrupt Assignment EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments 12. Local Interrupt Entry Fields Destination Local Apic IDDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Discrete Apic Configurations Default ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Default Configuration Interrupt Assignments Config INTINx CommentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAll Local APICs Config LINTINx Comments Assignment of System Interrupts to the Apic Local UnitEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingOther IPI Applications Spurious Apic InterruptsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Bus Entries in Systems with More Than One PCI Bus I/O Interrupt Assignment Entries for PCI DevicesMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry14. System Address Space Mapping Entry Fields Entry LengthAddress Type Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number
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