Intel MultiProcessor Base MP Configuration Table Entries, MP Configuration Table Header Fields

Page 42

MultiProcessor Specification

Table 4-2. MP Configuration Table Header Fields

 

Offset

Length

 

 

 

Field

(in bytes)

(in bits)

Description

 

 

 

 

 

 

SIGNATURE

0

32

The ASCII string representation of “PCMP,” which

 

 

 

confirms the presence of the table.

 

 

 

 

 

 

BASE TABLE LENGTH

4

16

The length of the base configuration table in bytes,

 

 

 

including the header, starting from offset 0. This field

 

 

 

aids in calculation of the checksum.

 

 

 

 

SPEC_REV

6

8

The version number of the MP specification. A value

 

 

 

 

 

 

 

 

 

of 01h indicates Version 1.1. A value of 04h indicates

 

 

 

Version 1.4.

 

 

 

 

CHECKSUM

7

8

A checksum of the entire base configuration table. All

 

 

 

bytes, including CHECKSUM and reserved bytes,

 

 

 

must add up to zero.

 

 

 

 

OEM ID

8

64

A string that identifies the manufacturer of the system

 

 

 

hardware.

 

 

 

 

PRODUCT ID

16

96

A string that identifies the product family.

 

 

 

 

OEM TABLE POINTER

28

32

A physical-address pointer to an OEM-defined

 

 

 

configuration table. This table is optional. If not

 

 

 

present, this field is zero.

 

 

 

 

OEM TABLE SIZE

32

16

The size of the base OEM table in bytes. If the table

 

 

 

is not present, this field is zero.

 

 

 

 

ENTRY COUNT

34

16

The number of entries in the variable portion of the

 

 

 

base table. This field helps the software identify the

 

 

 

end of the table when stepping through the entries.

 

 

 

 

ADDRESS OF LOCAL APIC

36

32

The base address by which each processor accesses

 

 

 

its local APIC.

 

 

 

 

EXTENDED TABLE

40

16

Length in bytes of the extended entries that are

LENGTH

 

 

located in memory at the end of the base

 

 

 

configuration table. A zero value in this field indicates

 

 

 

that no extended entries are present.

 

 

 

 

EXTENDED TABLE

42

8

Checksum for the set of extended table entries,

CHECKSUM

 

 

including only extended entries starting from the end

 

 

 

of the base configuration table. When no extended

 

 

 

table is present, this field is zero.

 

 

 

 

 

 

4.3Base MP Configuration Table Entries

A variable number of variable length entries follow the header of the MP configuration table. The first byte of each entry identifies the entry type. Each entry type has a known, fixed length. The total length of the MP configuration table depends upon the configuration of the system. Software must step through each entry in the base table until it reaches ENTRY COUNT. The entries are sorted on ENTRY TYPE in ascending order. Table 4-3 gives the meaning of each value of

ENTRY TYPE.

4-6

Version 1.4

Image 42
Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewFeatures of the Specification MultiProcessor SpecificationScope Document Organization Target AudienceOrganization of This Document IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries ApicProcessor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description CommentsBUS Type Bus EntriesBUS ID StringBus Type String Values Bus Type String DescriptionApic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/OEisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingHandling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space EntryAddress Type 14. System Address Space Mapping Entry FieldsEntry Length Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number