Intel MultiProcessor manual 126

Page 90

MultiProcessor Specification

Table 4-1. MP Floating Pointer Structure Fields

 

Offset

Length

 

Field

(in bytes:bits)

(in bits)

Description

 

 

 

 

SIGNATURE

0

32

The ASCII string represented by “_MP_” which

 

 

 

serves as a search key for locating the pointer

 

 

 

structure.

 

 

 

 

PHYSICAL ADDRESS

4

32

The address of the beginning of the MP

POINTER

 

 

configuration table. All zeros if the MP

 

 

 

configuration table does not exist.

 

 

 

 

LENGTH

8

8

The length of the floating pointer structure table

 

 

 

in paragraph (16-byte) units. The structure is 16

 

 

 

bytes or 1 paragraph long; so this field contains

 

 

 

01h.

 

 

 

 

SPEC_REV

9

8

The version number of the MP specification

 

 

 

supported. A value of 01h indicates Version 1.1.

 

 

 

A value of 04h indicates Version 1.4.

 

 

 

 

CHECKSUM

10

8

A checksum of the complete pointer structure.

 

 

 

All bytes specified by the length field, including

 

 

 

CHECKSUM and reserved bytes, must add up to

 

 

 

zero.

 

 

 

 

MP FEATURE

11

8

Bits 0-7:MP System Configuration Type.

INFORMATION BYTE 1

 

 

When these bits are all zeros, the MP

 

 

 

configuration table is present. When nonzero,

the value indicates which default configuration (as defined in Chapter 5) is implemented by the system.

MP FEATURE

12:0

6

INFORMATION BYTE 2

12:6

1

12:71

Bits 0-5:Reserved for future MP definitions.

Bit 6: Multiple Clock Sources. When set, this bit indicates that the processors derive clock signals from different sources. Otherwise when not set this bit indicates that all processors share a single clock source.

Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented.

MP FEATURE

13

24

Reserved for future MP definitions. Must be

INFORMATION BYTES 3-5

 

 

zero.

 

 

 

 

The MP feature information byte 1 specifies the MP system default configuration type. If nonzero, the system configuration conforms to one of the default configurations. The default configurations, specified in Chapter 5, may only be used to describe systems that always have two processors installed.

Bit 6 of MP feature information byte 2, the Multiple Clock Source bit, is used by the operating system to determine how processors derive clock sources. If the system design does not provide

for a single clock source shared by all processors then this bit is set. Otherwise this bit is zero to

indicate that all processors derive their clock from a common source. Bit 7 of MP feature

E-2

Version 1.4

Image 90
Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewFeatures of the Specification MultiProcessor SpecificationScope Document Organization Target AudienceOrganization of This Document IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries ApicProcessor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description CommentsBUS Type Bus EntriesBUS ID StringBus Type String Values Bus Type String DescriptionApic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/OEisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingHandling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space EntryAddress Type 14. System Address Space Mapping Entry FieldsEntry Length Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number