Intel MultiProcessor manual Hardware Overview, System Processors

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MultiProcessor Specification

CPU

CPU

CPU

HIGH-BANDWIDTH MEMORY BUS

ICC BUS

SHARED		GRAPHICS
MEMORY		FRAME
MODULE		BUFFER

APIC ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER

APIC

I/O

INTERFACE

APIC

I/O

INTERFACE

ICC INTERRUPT CONTROLLER	I/O EXPANSION BUS	I/O EXPANSION BUS
COMMUNICATIONS

Figure 2-1. Multiprocessor System Architecture

2.1 Hardware Overview

The MP specification defines a system architecture based on the following hardware components:

∙One or more processors that are Intel architecture instruction set compatible, such as the CPUs in the Intel486 and the Pentium processor family.

∙One or more APICs, such as the Intel 82489DX Advanced Programmable Interrupt Controller or the integrated APIC on the Pentium 735\90 and 815\100 processors.

∙Software-transparent cache and shared memory subsystem.

∙Software-visible components of the PC/AT platform.

2.1.1System Processors

To maintain compatibility with existing PC/AT software products, this specification is based on the Intel486 and the Pentium processor family. To achieve a minimum level of MP system performance, two or more processors that are Intel architecture instruction set compatible are required.

Figure 2-2 gives a different point of view of a compliant system, showing the configuration of the APICs with respect to the CPUs. While all processors in a compliant system are functionally identical, this specification classifies them into two types: the bootstrap processor (BSP) and the application processors (AP). Which processor is the BSP is determined by the hardware or by the hardware in conjunction with the BIOS. This differentiation is for convenience and is in effect

2-2	Version 1.4

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewMultiProcessor Specification Features of the SpecificationScope Target Audience Organization of This DocumentDocument Organization IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingMultiprocessor Interrupt Control Posted Memory WriteApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeFloating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description MP Feature Offset Length Field Bytesbits Bits DescriptionInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderMP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Base MP Configuration Table Entry Types Processor EntriesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Feature Flags from Cpuid Instruction Intel486 and Pentium Processor SignaturesFamily Model Stepping a Description Bit Name Description CommentsBus Entries BUS IDBUS Type StringBus Type String Values Bus Type String Description3 I/O Apic Entries 4 I/O Interrupt Assignment EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments 12. Local Interrupt Entry Fields Destination Local Apic IDDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Discrete Apic Configurations Default ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Default Configuration Interrupt Assignments Config INTINx CommentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAll Local APICs Config LINTINx Comments Assignment of System Interrupts to the Apic Local UnitEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingOther IPI Applications Spurious Apic InterruptsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Bus Entries in Systems with More Than One PCI Bus I/O Interrupt Assignment Entries for PCI DevicesMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry14. System Address Space Mapping Entry Fields Entry LengthAddress Type Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number