Intel MultiProcessor manual Errata

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Errata

The following sections provided here are intended to replace the corresponding sections in the main body of the specification. The sections provided here are shown in their entirety to provide context for the changes. Changes contained below are marked with double underlined text which shows changes relative to the version of the sections that are provided in the main body of the specification.

4.1MP Floating Pointer Structure

An MP-compliant system must implement the MP floating pointer structure, which is a variable length data structure in multiples of 16 bytes. Currently, only one 16-byte data structure is defined. It must span a minimum of 16 contiguous bytes, beginning on a 16-byte boundary, and it must be located within the physical address as specified in the previous section. To determine whether the system conforms to the MP specification, the operating system must search for the MP floating pointer structure in the order specified in the previous section. Figure 4-2 shows the format of this structure, and Table 4-1 explains each of the fields.

	31	24 23			16 15		8	7		0
					MP FEATURE						0CH
					BYTES 2-5						0CH
					BYTES 2-5

		MP FEATURE			CHECKSUM		SPEC_REV		LENGTH		08H
		BYTE 1			CHECKSUM		SPEC_REV		LENGTH		08H
		BYTE 1

					PHYSICAL ADDRESS POINTER						04H

					SIGNATURE						00H
		_ (5Fh)			P (50h)		M (4Dh)		_ (5Fh)		00H
		_ (5Fh)			P (50h)		M (4Dh)		_ (5Fh)

	31	24 23			16 15		8	7		0

Figure 4-2. MP Floating Pointer Structure

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables FiguresExamples Page Conceptual Overview GoalsScope Features of the SpecificationMultiProcessor Specification Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemApic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeApic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderOffset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number