Intel MultiProcessor manual Other IPI Applications, Spurious Apic Interrupts, Handling Cache Flush

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MultiProcessor Specification

of an INIT IPI used to shut down an AP. As a result, the operating system must ensure that any required state information is captured and that caches are flushed as necessary before sending the

INIT IPI.

In order to do a complete system shutdown, followed by a warm restart if necessary, the operating system should return the system to a state similar to that at power-on. This includes disabling the Local APIC interrupts (LINT0/LINT1/Local APIC Timer/Error interrupt) on all processors, disabling the Local APIC on all APs and disabling all interrupts at all the I/O APICs in the system. The operating system can use an IPI or an NMI to signal to all APs for per-processor shutdown handling. The operating system may then set the CMOS shutdown code to 0Ah and perform a keyboard controller reset.

B.6 Other IPI Applications

The operating system may use IPIs for other run-time duties, such as handling the various processor caches.

B.6.1 Handling Cache Flush

The MP specification requires that hardware maintain cache coherency. Cache flushing by the operating system should not be required under normal circumstances. The only need for cache flushing by the operating system is prior to powering down a processor.

Should a system-wide cache flush be necessary, the operating system should use the broadcast IPI mechanism to request that each of the processors write back and invalidate its own cache subsystem and then synchronize upon the completion of that activity.

B.6.2 Handling TLB Invalidation

The operating system should use the IPI mechanism to request that each of the processors invalidate its TLBs. The operating system may use a broadcast IPI for this purpose. The BSP and APs should synchronize the completion of their actions either via memory-based semaphores or via targeted return IPIs. The actual IPI vector is operating system dependent.

B.6.3 Handling PTE Invalidation

The operating system should use the IPI mechanism to request that each processor invalidate a specific page-table entry (PTE) if it is cached in that processor’s TLBs. The operating system may use a broadcast IPI for this purpose. The BSP and APs should synchronize the completion of their actions either via memory-based semaphores or via targeted return IPIs. The actual IPI vector is operating system dependent.

B.7 Spurious APIC Interrupts

For the 8259, there is a time window in which a spurious interrupt may be misinterpreted as a genuine interrupt. For example, if an interrupt goes inactive just after the first INTA cycle but before the second INTA cycle, the 8259 will also signal this spurious interrupt as a genuine

B-6

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Figures TablesExamples Page Goals Conceptual OverviewScope Features of the SpecificationMultiProcessor Specification Target Audience Organization of This DocumentDocument Organization IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingApic Architecture Posted Memory WriteMultiprocessor Interrupt Control Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeApic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure MP Feature Offset Length Field Bytesbits Bits DescriptionInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderOffset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Base MP Configuration Table Entry Types Processor EntriesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Feature Flags from Cpuid Instruction Intel486 and Pentium Processor SignaturesFamily Model Stepping a Description Bit Name Description CommentsBus Entries BUS IDBUS Type StringBus Type String Values Bus Type String Description3 I/O Apic Entries 4 I/O Interrupt Assignment EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values 12. Local Interrupt Entry Fields Destination Local Apic IDDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Discrete Apic Configurations Default ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Default Configuration Interrupt Assignments Config INTINx CommentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAll Local APICs Config LINTINx Comments Assignment of System Interrupts to the Apic Local UnitEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingOther IPI Applications Spurious Apic InterruptsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Bus Entries in Systems with More Than One PCI Bus I/O Interrupt Assignment Entries for PCI DevicesMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry14. System Address Space Mapping Entry Fields Entry LengthAddress Type Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number
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