Intel MultiProcessor manual Extended MP Configuration Table Entries

Page 53

MP Configuration Table

4.4Extended MP Configuration Table Entries

A variable number of variable-length entries are located in memory, immediately following entries in the base section of the MP configuration table described in Section 4.3. These entries compose the extended section of the MP configuration table. Each entry in the extended section of the table has three elements:

∙ENTRY TYPE

∙ENTRY LENGTH

∙DATA

ENTRY TYPE and ENTRY LENGTH make up a header that is present in all extended configuration table entries. The ENTRY TYPE and ENTRY LENGTH fields are eight bit unsigned values. ENTRY LENGTH specifies the total length of the given configuration entry. The length of the DATA field is two bytes less than the value specified by ENTRY LENGTH.

This scheme ensures that operating systems can parse all the entries in the extended MP configuration table area, even if an entry type is unrecognized. Operating systems that find an unknown entry type when parsing this section of the table should ignore the content and move on to the next entry, until the offset from the end of the base table reaches the length that is specified in the EXTENDED TABLE LENGTH field of the configuration table header. The ability to skip entries with unrecognized type codes beyond those listed in Table 4-13is essential since it is anticipated that more types of entries will be added to this list over time.

The total length of the Extended MP configuration table depends upon the configuration of the system. The entries are sorted on ENTRY TYPE in ascending order. Table 4-13 gives the meaning of each value of ENTRY TYPE.

Table 4-13. Extended MP Configuration Table Entry Types

	Entry Type	Length
Entry Description	Code*	(in bytes)	Comments

SYSTEM ADDRESS SPACE	128	20	Entry to declare system visible memory
MAPPING			or I/O space on a bus.

BUS HIERARCHY DESCRIPTOR	129	8	Entry to describe I/O bus interconnection.

COMPATIBILITY BUS ADDRESS	130	8	Entry to describe predefined address
SPACE MODIFIER			ranges that modify the memory or I/O
			space visible on a bus in order to support
			ISA compatibility.

*All other type codes are reserved.

Version 1.4

4-17

Image 53

Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables FiguresExamples Page Conceptual Overview GoalsScope Features of the SpecificationMultiProcessor Specification Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemApic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeApic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderOffset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number