Intel MultiProcessor manual Default Configuration for Discrete Apic, Default Configurations

Page 63

Default Configurations

A

IMCR

E0

BSP

INTEL486™

CPU 1

NMI INTR RESET

AP2

INTEL486™

CPU 3

NMI INTR RESET

 

PNMI

PINT

PRST ExtINTA

PNMI

PINT

PRST ExtINTA

 

 

 

LOCAL

 

 

 

LOCAL

 

 

 

 

 

REG.

 

82489DX APIC

INTA

82489DX APIC

 

INTA

 

MARK

LINTIN0

LINTIN1

TRAP

LINTIN0

LINTIN1

TRAP

 

 

 

 

 

NMI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NMI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ1

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

B

 

 

 

 

 

3

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

8254 TIMER

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

IRQ8#

 

 

8

 

 

 

 

 

7

82489DX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

8

 

APIC

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

10

 

 

 

10

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

IRQ13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

EISA DMA CHAINING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GLUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FROM BSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FERR#

FERR

 

 

 

 

 

 

 

 

0

 

 

 

 

IGNNE#

 

 

 

 

 

 

 

 

 

 

 

 

SAMPLING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

3

 

 

 

32

MASTER

INTR

 

 

 

 

 

 

4

 

 

 

4

8259A PIC

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

ABFULL

ABFULL

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

12

 

 

 

7

 

 

 

 

(PS/2 MOUSE) SAMPLING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTA

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

0

 

 

 

 

EDGE/LEVEL TRIGGER

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

POLARITY CONTROL

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

11

 

 

 

 

SLAVE

 

IRQ3-7,

 

 

 

 

 

 

 

 

 

3

 

 

IRQx

 

 

 

 

 

 

 

 

4

8259A PIC

 

9-12,14,15

 

 

 

 

14

 

 

 

5

 

 

 

 

 

LITMx

 

 

 

 

 

 

 

6

 

 

 

 

LITM3-7,

 

12

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9-12,14,15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHADED AREAS:

A: OPTIONAL IF VIRTUAL WIRE MODE IS IMPLEMENTED

B,C: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS

C,D: EISA BUS SPECIFIC

Figure 5-1. Default Configuration for Discrete APIC

Version 1.4

5-3

Page 62 Page 64
Image 63
Page 62 Page 64
Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsFeatures of the Specification MultiProcessor SpecificationScope Introduction Target AudienceOrganization of This Document Document OrganizationFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information ByteMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes CommentsProcessor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a DescriptionString Bus EntriesBUS ID BUS TypeBus Type String Description Bus Type String ValuesI/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic EntryI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local ApicExtended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number BusDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O UnitLevel-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13MultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPIHandling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache FlushSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping EntriesAddress Base 14. System Address Space Mapping Entry FieldsEntry Length Address TypeSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number
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