Intel MultiProcessor manual AP Shutdown Handling, Using Startup IPI

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Operating System Programming Guidelines

By putting an appropriate pointer in the warm-reset vector, setting the shutdown code to 0Ah, then causing an INIT, the BIOS (or the operating system) can cause the current processor to jump immediately to any location. Because all processors in an MP system share the same system memory, and because the INIT IPI gives one processor the power to cause an INIT at another, the operating system can cause any processor to jump immediately to any location.

B.4.2 USING STARTUP IPI

STARTUP IPIs are used with systems based on Intel processors with local APIC versions of 1.x or higher. These local APICs recognize the STARTUP IPI, which is an APIC Interprocessor Interrupt with trigger mode set to edge and delivery mode set to “110” (bits 8 through 10 of the ICR).

The STARTUP IPI causes the target processor to start executing in Real Mode from address 000VV000h, where VV is an 8-bit vector that is part of the IPI message. Startup vectors are limited to a 4-kilobyte page boundary in the first megabyte of the address space. Vectors A0-BF are reserved; do not use vectors in this range. STARTUP IPIs are not maskable, do not cause any change of state in the target processor (except for the change to the instruction pointer), and can be issued only one time after RESET or after an INIT IPI reception or pin assertion. A STARTUP IPI neither requires the targeted APIC to be enabled nor the interrupt table to be programmed. If the target processor is in the halted state immediately after RESET or INIT, a STARTUP IPI causes it to leave that state and start executing. The effect is to set CS:IP to VV00:0000h.

For an operating system to use a STARTUP IPI to wake up an AP, the address of the AP initialization routine (or of a branch to that routine) must be in the form of 000VV000h. Sending a STARTUP IPI with VV as its vector causes the AP to jump immediately to and begin executing the operating system’s AP initialization routine.

The operating system should not issue a STARTUP IPI to an 82489DX since the STARTUP IPI will be ignored instead of forcing the targeted processor to execute from the given address.

B.5 AP Shutdown Handling

An AP may be shut down by itself, by the BSP, or by another active AP. Shutting down an AP with an active task or a bound device driver is not permitted. Only the BSP may shut itself down, and it must be the last processor to shut down.

There are several possible alternatives for shutdown handling. Two of the possibilities are presented here by way of example.

In the simplest case, the operating system can define an IPI for shutting down and taking APs off- line. The exact usage and behavior of an IPI that is defined for this purpose is operating system specific and is not defined in this specification.

Should the BSP need to take an AP off-line or to place the AP back into a HALT state, the BSP can also use the INIT IPI with Warm Restart. The operating system places the address of a HLT instruction in the warm-reset vector (40:67), sets the CMOS shut-down code to 0Ah, then sends an INIT IPI to the AP. The INIT IPI causes the AP to enter the BIOS POST routine, where it immediately jumps to the warm-reset vector and executes the operating system’s HLT instruction. Only one processor can execute the shutdown routine at any given time, due to the use of the shutdown code. The operating system must not rely on any code being executed after the delivery

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsMultiProcessor Specification Features of the SpecificationScope Introduction Target AudienceOrganization of This Document Document OrganizationFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemMultiprocessor Interrupt Control Posted Memory WriteApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeFloating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information ByteMP Configuration Table Header MP Configuration Table HeaderMP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes CommentsProcessor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a DescriptionString Bus EntriesBUS ID BUS TypeBus Type String Description Bus Type String ValuesI/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic EntryI/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local ApicExtended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number BusDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O UnitLevel-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13MultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPIHandling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache FlushSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping EntriesAddress Base 14. System Address Space Mapping Entry FieldsEntry Length Address TypeSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number