Intel MultiProcessor manual System Memory, 4 I/O Expansion Bus

Page 18

MultiProcessor Specification

The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to interrupt any other processor or set of processors. There are several types of IPIs. Among them, the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown.

Each local APIC has a Local Unit ID Register and each I/O APIC has an I/O Unit ID Register. The ID serves as a physical name for each APIC unit. It is used by software to specify destination information for I/O interrupts and interprocessor interrupts, and is also used internally for accessing the ICC bus.

Due to the distributed architecture, the APIC local and I/O units can be implemented in either a single chip, such as Intel’s 82489DX interrupt controller, or they can be integrated with other parts of the system’s components. For example, the local APIC may be integrated with the CPU chip, such as Intel’s Pentium processors (735\90, 815\100), and the I/O APIC may be integrated with the I/O chipset, such as Intel’s 82430 PCI-EISA bridge chipset.

2.1.3System Memory

A system that complies with the MP specification uses the standard AT memory architecture. All memory is allocated for system memory with the exception of addresses 0A_0000h through

0F_FFFFh and 0FFFE_0000h through 0FFFF_FFFFh, which are reserved for I/O devices and the BIOS.

Compared to a uniprocessor system, a symmetric multiprocessor system imposes a high demand for memory bus bandwidth. The demand is proportional to the number of processors on the memory bus. To reduce memory bus bandwidth limitations, an implementation of this specification should use a secondary cache that has high-performance features, such as a write-back update policy and a snooping cache-consistency protocol. A secondary cache can push the scalability limit upward by reducing bus traffic and increasing bus bandwidth.

While both secondary caches and memory bus controllers are critical components for high performance in a symmetric multiprocessor system, this specification does not detail their implementation, requiring only that they be totally software transparent.

2.1.4I/O Expansion Bus

The MP specification provides a multiprocessor extension to the industry-standard PC/AT platform. The term “industry-standard PC/AT platform” here refers to the software-visible components of the PC/AT. The standard does not designate a specific bus architecture. All industry-standard buses, such as ISA, EISA, MCA, VL, and PCI, can be incorporated in the design. Systems developers can implement one or more bus types in their designs, depending on the systems’ I/O performance or capacity requirements.

2-4

Version 1.4

Page 17 Page 19
Image 18
Page 17 Page 19
Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewFeatures of the Specification MultiProcessor SpecificationScope Document Organization Target AudienceOrganization of This Document IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries ApicProcessor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description CommentsBUS Type Bus EntriesBUS ID StringBus Type String Values Bus Type String DescriptionApic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/OEisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingHandling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space EntryAddress Type 14. System Address Space Mapping Entry FieldsEntry Length Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number
Top Page Image Contents