Intel Comprehensive Guide to APIC Hardware Specifications
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Hardware Specification

3.6.6APIC Identification

Systems developers must assign APIC local unit IDs and ensure that all are unique. There are two acceptable ways to assign local APIC IDs, as follows:

∙By hardware. The ID of each APIC local unit is sampled from the appropriate pins at RESET.

∙By the BIOS. Software can override the APIC IDs assigned by hardware by writing to the Local Unit ID Register. This is possible only with help from the hardware; for example, using board ID registers that the software can read to determine which board has the BSP.

Local APIC IDs must be unique, and need not be consecutive.

The MP operating system can use the local APIC ID to determine on which processor it is executing.

The ID of each I/O APIC unit is set to zero during RESET. It is the responsibility of the operating system to verify the uniqueness of the I/O APIC ID and to assign a unique ID if a conflict is found. The assignment of APIC IDs for I/O units must always begin from the lowest number that is possible after the assignment of local APIC IDs. The operating system must not attempt to change the ID of an APIC I/O unit if the preset ID number is acceptable.

3.6.7APIC Interval Timers

The 82489DX APIC local unit contains a 32-bit wide programmable timer with the following two independent clock input sources:

1.The CLK pin provides the clock signal that drives the 82489DX APIC’s internal operation.

2.The TMBASE pin allows an independent clock signal to be connected to the 82489DX APIC for use by the timer functions.

The interval timers of the integrated APIC have only one clock input source, CLK. To maintain consistency, developers of compliant systems based on the 82489DX must choose CLK as the source of the 82489DX APIC timer clock. TMBASE must be left disabled. An MP operating system may use the IRQ8 real-time clock as a reference to determine the actual APIC timer clock speed.

Special consideration must be made for systems with stop clock (STPCLK#) capability. Timer interrupts are ignored while STPCLK# is asserted. The system time-of-day clock may need to be reset when STPCLK# is deasserted.

3.6.8Multiple I/O APIC Configurations

Systems may provide more than one I/O APIC for increased interrupt scalability in Symmetric I/O Mode. To preserve PC/AT compatibility in PIC or Virtual Wire mode, interrupts connected to additional I/O APICs must also be connected to the 8259A programmable interrupt controller. Figure 3-6 represents one possible interrupt connection scheme for a system with two I/O APICs.

The non-ISA interrupts are connected to both the 8259A IRQ inputs and the inputs of the associated I/O APIC. To prevent non-ISA interrupts from appearing at inputs on both I/O APICs, the hardware must provide a means to disable the interrupt routing network when the system switches to symmetric I/O mode with the second I/O APIC enabled.

More information about the implementation of multiple I/O APIC configurations is presented in Appendix D.

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsFeatures of the Specification MultiProcessor SpecificationScope Organization of This Document Target AudienceDocument Organization IntroductionFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description CommentsBUS ID Bus EntriesBUS Type StringBus Type String Description Bus Type String Values4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAssignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPISpurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping EntriesEntry Length 14. System Address Space Mapping Entry FieldsAddress Type Address BaseSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number
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