Intel MultiProcessor manual Processor Entries, Base MP Configuration Table Entry Types, Apic

			MP Configuration Table
Table 4-3. Base MP Configuration Table Entry Types
		Length
Entry Description	Entry Type Code*	(in bytes)	Comments
Processor	0	20	One entry per processor.
Bus	1	8	One entry per bus.
I/O APIC	2	8	One entry per I/O APIC.
I/O Interrupt Assignment	3	8	One entry per bus interrupt source.
Local Interrupt Assignment	4	8	One entry per system interrupt
			source.

*All other type codes are reserved.

4.3.1Processor Entries

Figure 4-4 shows the format of each processor entry, and Table 4-4 defines the fields.

31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0

RESERVED

RESERVED

FEATURE FLAGS

CPU SIGNATURE

	CPU FLAGS			LOCAL APIC		LOCAL APIC ID				ENTRY TYPE
		B E		VERSION #							0
RESERVED		P	N
31	28 27	24 23		20 19	16 15		12 11	8	7	4	3	0

10H

0CH

08H

04H

00H

Figure 4-4. Processor Entry

In systems that use the MP configuration table, the only restriction placed on the assignment of APIC IDs is that they be unique. They do not need to be consecutive. For example, it is possible for only APIC IDs 0, 2, and 4 to be present.

Version 1.4 4-7