Intel MultiProcessor manual Operating System Booting and Self-configuration

Page 76

MultiProcessor Specification

The operating system’s first task is to determine whether the system conforms to the MP specification. This is done by searching for the MP floating pointer structure. If a valid floating pointer structure is detected, it indicates that the system is MP-compliant, and the operating system should continue to look for the MP configuration table. If the system is not MP-compliant, the operating system may attempt other means of MP system detection, if it is capable of doing so, or treat the system as a uniprocessor system.

B.2 Operating System Booting and Self-configuration

An MP configuration table is required by the MP specification, with the exception of the default system configurations defined in Chapter 5. The table should be treated as read-only by the operating system. If the MP configuration table exists, the BSP should access the processor entries in the table to configure the operating system.

The BSP should later configure the operating system based on the bus, I/O APIC, IRQs, and system interrupt assignment entries of the configuration table. Note that certain types of buses are mutually exclusive, such as EISA with MCA, or ISA with MCA. The operating system may report such errors in the configuration table, if they occur.

If the MP configuration table does not exist, the BSP configures the operating system for the default system configuration indicated by the default configuration bits of the MP feature information bytes. In this case, only two processors and one I/O APIC exist in the system; both processors have the same type and features.

The operating system contains a set of predefined internal configuration tables that represent the default configurations described in Chapter 5. For MP-compliant systems that use one of the default configurations, the operating system derives the required configuration information from the corresponding predefined table.

To wake up the AP, the BSP should use the universal algorithm defined in Section B.4.

B.3 Interrupt Mode Initialization and Handling

At the time the operating system boots, the interrupt structure is configured for DOS compatibility. The system may be running either in PIC Mode or in Virtual Wire Mode. If it is in PIC Mode, the NMI and INTR will bypass the BSP’s local APIC when the Interrupt Mode Configuration Register (IMCR) has a value of zero. The operating system should not try to read the IMCR because it may not exist.

The operating system should switch over to Symmetric I/O Mode to start multiprocessor operation. If the IMCRP bit of the MP feature information bytes is set, the operating system must set the IMCR to APIC mode. The operating system should not write to the IMCR unless the IMCRP bit is set.

B-2

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewMultiProcessor Specification Features of the SpecificationScope Target Audience Organization of This DocumentDocument Organization IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingMultiprocessor Interrupt Control Posted Memory WriteApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeFloating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description MP Feature Offset Length Field Bytesbits Bits DescriptionInformation Byte Information BytesMP Configuration Table Header MP Configuration Table HeaderMP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Base MP Configuration Table Entry Types Processor EntriesLength Entry Description Entry Type Code Bytes Comments ApicProcessor Entry Fields Feature Flags from Cpuid Instruction Intel486 and Pentium Processor SignaturesFamily Model Stepping a Description Bit Name Description CommentsBus Entries BUS IDBUS Type StringBus Type String Values Bus Type String Description3 I/O Apic Entries 4 I/O Interrupt Assignment EntriesApic Entry I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments 12. Local Interrupt Entry Fields Destination Local Apic IDDestination Local Apic LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Discrete Apic Configurations Default ConfigurationsDefault Number Bus Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Default Configuration Interrupt Assignments Config INTINx CommentsAssignment of I/O Interrupts to the Apic I/O Unit First I/OAll Local APICs Config LINTINx Comments Assignment of System Interrupts to the Apic Local UnitEisa and IRQ13 Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingOther IPI Applications Spurious Apic InterruptsHandling Cache Flush Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Bus Entries in Systems with More Than One PCI Bus I/O Interrupt Assignment Entries for PCI DevicesMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry14. System Address Space Mapping Entry Fields Entry LengthAddress Type Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number
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