Intel MultiProcessor manual Assignment of System Interrupts to the Apic Local Unit, Eisa and IRQ13

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Default Configurations

Certain EISA chipsets do not bring out the IRQ0, 8254 timer interrupt, and IRQ13 EISA DMA chaining interrupt signals. If these signals are not directly available, INTIN2 and INTIN13 should be disabled. Refer to Section 5.3.1 for more details.

5.3.1EISA and IRQ13

IRQ13 is a shared interrupt as defined in the EISA bus specification. Because a compliant system supports only the on-chip floating point unit, IRQ13 carries only the EISA chaining interrupt.

If IRQ13 is not connected to the I/O APIC, the EISA chaining interrupt may be handled as a mixed-mode operation. Mixed mode means that the APIC and 8259A-equivalent PIC are connected in a cascading manner via INTIN0, and INTIN0 is programmed for ExtINT and edge- triggered mode. If all other interrupts are masked off in the PIC, INTIN0 only receives the DMA chaining interrupt.

An MP operating system should disable the I/O APIC INTIN13 and configure the I/O APIC to mixed mode if the EISA DMA chaining signal is not available at the I/O APIC.

5.3.2Level-triggered Interrupt Support

Several AT-compatible buses, such as EISA and MCA, support active-low, level-triggered interrupts. If these types of buses are to be incorporated in a compliant system, external inverters must be implemented to ensure that signals presented to the 82489DX APIC are active-high and level-triggered. See Section 4.3.4 on I/O Interrupt Assignment Flags.

For EISA implementations, the external interrupt polarity control inverters must be controlled by the EISA edge/level-triggered polarity control registers (4D0h-4D1h). MCA does not have this register. To convert an active-high trigger to an active-low trigger, an inverter for each interrupt line must be implemented.

5.4 Assignment of System Interrupts to the APIC Local Unit

The APIC local unit has two general-purpose interrupt inputs that are reserved for system interrupts. Table 5-3 shows how the interrupt request line (IRQ) assignments are connected to the local APIC in each of the default configurations.

Table 5-3 Assignment of System Interrupts to APIC Local Unit

All Local
APICs	Config	Config	Config	Config	Config	Config	Config
LINTINx	1	2	3	4	5	6	7	Comments

LINTIN0	8259A	8259A	8259A	8259A	8259A	8259A	8259A	INTR output from
	INTR	INTR	INTR	INTR	INTR	INTR	INTR	master 8259A or
								equivalent

LINTIN1	NMI	NMI	NMI	NMI	NMI	NMI	NMI	Nonmaskable
								interrupt

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page Conceptual Overview GoalsMultiProcessor Specification Features of the SpecificationScope Introduction Target AudienceOrganization of This Document Document OrganizationFor More Information Conventions Used in This DocumentSystem Overview System Processors Hardware OverviewSystem Overview Advanced Programmable Interrupt Controller4 I/O Expansion Bus System MemoryOperating System Overview Bios OverviewPage System Memory Configuration Hardware SpecificationSystem Memory Address Map System Memory Cacheability and ShareabilityMemory Cacheability Map Hardware SpecificationLocking External Cache SubsystemMultiprocessor Interrupt Control Posted Memory WriteApic Architecture Apic Versions Interrupt ModesPIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire ModeVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeFloating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Identification Apic Interval TimersSystem-wide Reset Reset SupportProcessor-specific Init System-wide InitSystem Initial State Support for Fault-resilient BootingMP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information ByteMP Configuration Table Header MP Configuration Table HeaderMP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes CommentsProcessor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a DescriptionString Bus EntriesBUS ID BUS TypeBus Type String Description Bus Type String ValuesI/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic EntryI/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local ApicExtended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number BusDefault Configurations Default Configuration for Discrete ApicIntegrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O UnitLevel-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13MultiProcessor Specification Bios Post Initialization System Bios Programming GuidelinesControlling the Application Processors Programming the Apic for Virtual Wire ModeSystem Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire ModeNMI Constructing the MP Configuration TableSystem Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-upInterrupt Mode Initialization and Handling Operating System Booting and Self-configurationOperating System Programming Guidelines Application Processor StartupUsing Init IPI AP Shutdown Handling Using Startup IPIHandling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache FlushSupporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICsFixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping EntriesAddress Base 14. System Address Space Mapping Entry FieldsEntry Length Address TypeSpace records must also be provided Bus Hierarchy Descriptor EntryParent BUS BUS InformationsdGlossary Glossary-2 Order Number