Intel MultiProcessor manual Assignment of I/O Interrupts to the Apic I/O Unit, First I/O

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MultiProcessor Specification

should be cross-connected between the BSP and AP processors. Although the INIT pin is cross- connected between BSP and AP, a targeted INIT IPI initializes only the targeted processor, because the INIT IPI does not cause the INIT pin to change state.

The interconnection of I/O APIC interrupt lines is the same as for the 82489DX APIC configuration. However, for PCI system implementations based on the Intel PCI chipset, the PCI PIRQx lines are mapped to the ISA IRQx via a mapping register. This type of implementation makes PCI interrupt lines appear as ISA interrupt lines, which are transparent to the operating system. All PCI systems defined in the default configurations are of this type. No I/O interrupt assignment entries are declared for PCI interrupts, as described in Section 4.3.4.

5.3 Assignment of I/O Interrupts to the APIC I/O Unit

The typical APIC I/O unit has 16 general-purpose interrupt inputs. Table 5-2 shows how the interrupt request line (IRQ) assignments are connected to the I/O APIC in each of the default configurations.

Table 5-2. Default Configuration Interrupt Assignments

First I/O
APIC	Config	Config	Config	Config	Config	Config	Config
INTINx	1	2	3	4	5	6	7	Comments

INTIN0	8259A	8259A	8259A	8259A	8259A	8259A	N/C	INTR output from
	INTR	INTR	INTR	INTR	INTR	INTR		master 8259A or
								equivalent

INTIN1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	Keyboard controller
								buffer full

INTIN2	IRQ0	N/C	IRQ0	IRQ0	IRQ0	IRQ0	IRQ0	8254 Timer

INTIN3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3

INTIN4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4

INTIN5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5

INTIN6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6

INTIN7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7

INTIN8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	Real time clock

INTIN9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9

INTIN10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10

INTIN11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11

INTIN12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12

INTIN13	IRQ13	N/C	IRQ13	IRQ13	IRQ13	IRQ13	IRQ13	Floating point
								exception and
								DMA chaining

INTIN14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14

INTIN15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15

NOTE:

N/C designates not connected.

5-6	Version 1.4

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Contents MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page Goals Conceptual OverviewFeatures of the Specification MultiProcessor SpecificationScope Document Organization Target AudienceOrganization of This Document IntroductionConventions Used in This Document For More InformationSystem Overview Hardware Overview System ProcessorsAdvanced Programmable Interrupt Controller System OverviewSystem Memory 4 I/O Expansion BusBios Overview Operating System OverviewPage Hardware Specification System Memory ConfigurationSystem Memory Cacheability and Shareability System Memory Address MapHardware Specification Memory Cacheability MapExternal Cache Subsystem LockingPosted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic VersionsPIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local ApicVirtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O ModeAssignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic IdentificationReset Support System-wide ResetSystem-wide Init Processor-specific InitSupport for Fault-resilient Booting System Initial StateMP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information BytesMP Configuration Table Header MP Configuration Table HeaderBase MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries ApicProcessor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description CommentsBUS Type Bus EntriesBUS ID StringBus Type String Values Bus Type String DescriptionApic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry FieldsI/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN#Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant SchematicDefault Configuration for Discrete Apic Default ConfigurationsIntegrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/OEisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt SupportMultiProcessor Specification System Bios Programming Guidelines Bios Post InitializationProgramming the Apic for Virtual Wire Mode Controlling the Application ProcessorsExample A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming GuidelinesConstructing the MP Configuration Table NMISystem Bios Programming Guidelines Page Operating System Boot-up Operating System Programming GuidelinesOperating System Booting and Self-configuration Interrupt Mode Initialization and HandlingApplication Processor Startup Operating System Programming GuidelinesUsing Init IPI Using Startup IPI AP Shutdown HandlingHandling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB InvalidationSupporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt RoutingFixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space EntryAddress Type 14. System Address Space Mapping Entry FieldsEntry Length Address BaseBus Hierarchy Descriptor Entry Space records must also be providedBUS Informationsd Parent BUSGlossary Glossary-2 Order Number