Philips P89LPC908, P89LPC906, P89LPC907 Mnemonic Description Bytes Cycles Hex Code, Data Transfer

Page 100

 

Philips Semiconductors

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

 

 

 

 

 

 

INSTRUCTION SET

 

P89LPC906/907/908

 

 

 

 

 

 

 

 

 

 

 

 

 

Mnemonic

Description

Bytes

 

Cycles

Hex

 

 

 

 

 

code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANL dir,A

AND A to direct byte

2

 

1

52

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANL dir,#data

AND immediate to direct byte

3

 

2

53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL A,Rn

OR register to A

1

 

1

48-4F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL A,dir

OR direct byte to A

2

 

1

45

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL A,@Ri

OR indirect memory to A

1

 

1

46-47

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL A,#data

OR immediate to A

2

 

1

44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL dir,A

OR A to direct byte

2

 

1

42

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORL dir,#data

OR immediate to direct byte

3

 

2

43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL A,Rn

Exclusive-OR register to A

1

 

1

68-6F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL A,dir

Exclusive-OR direct byte to A

2

 

1

65

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL A, @Ri

Exclusive-OR indirect memory to A

1

 

1

66-67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL A,#data

Exclusive-OR immediate to A

2

 

1

64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL dir,A

Exclusive-OR A to direct byte

2

 

1

62

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XRL dir,#data

Exclusive-OR immediate to direct byte

3

 

2

63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR A

Clear A

1

 

1

E4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPL A

Complement A

1

 

1

F4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWAP A

Swap Nibbles of A

1

 

1

C4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL A

Rotate A left

1

 

1

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RLC A

Rotate A left through carry

1

 

1

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RR A

Rotate A right

1

 

1

03

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RRC A

Rotate A right through carry

1

 

1

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA TRANSFER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV A,Rn

Move register to A

1

 

1

E8-EF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV A,dir

Move direct byte to A

2

 

1

E5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV A,@Ri

Move indirect memory to A

1

 

1

E6-E7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV A,#data

Move immediate to A

2

 

1

74

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV Rn,A

Move A to register

1

 

1

F8-FF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV Rn,dir

Move direct byte to register

2

 

2

A8-AF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV Rn,#data

Move immediate to register

2

 

1

78-7F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV dir,A

Move A to direct byte

2

 

1

F5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV dir,Rn

Move register to direct byte

2

 

2

88-8F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV dir,dir

Move direct byte to direct byte

3

 

2

85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV dir,@Ri

Move indirect memory to direct byte

2

 

2

86-87

 

 

 

 

 

 

 

 

 

 

 

 

2003 Dec 8

100

Page 99 Page 101
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Page 99 Page 101
Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonBlock Diagram P89LPC906 KB Code FlashCPU Oscillator DividerBlock Diagram P89LPC907 UartByte Data RAM ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR CodeEnhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionCPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterLOW Power Select P89LPC906 High freqMed freq Low freqCPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Port latch dataINPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFnPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm CclkRC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVMChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesSFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsBreak Detect Framing ErrorBrgcon Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control registerPower Down Operation Watchdog Clock SourcePrescaler CLKWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, aFeatures Using Flash AS Data StorageGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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