Philips P89LPC906, P89LPC908, P89LPC907 user manual Reti, B8-BF, D8-DF, Miscellaneous, Nop

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	Philips Semiconductors					User’s Manual - Preliminary -

	INSTRUCTION SET				P89LPC906/907/908

		Mnemonic	Description	Bytes		Cycles	Hex
		Mnemonic	Description	Bytes		Cycles	code
							code

		ACALL addr 11	Absolute jump to subroutine	2		2	116F1

		LCALL addr 16	Long jump to subroutine	3		2	12

		RET	Return from subroutine	1		2	22

		RETI	Return from interrupt	1		2	32

		AJMP addr 11	Absolute jump unconditional	2		2	016E1

		LJMP addr 16	Long jump unconditional	3		2	02

		SJMP rel	Short jump (relative address)	2		2	80

		JC rel	Jump on carry = 1	2		2	40

		JNC rel	Jump on carry = 0	2		2	50

		JB bit,rel	Jump on direct bit = 1	3		2	20

		JNB bit,rel	Jump on direct bit = 0	3		2	30

		JBC bit,rel	Jump on direct bit = 1 and clear	3		2	10

		JMP @A+DPTR	Jump indirect relative DPTR	1		2	73

		JZ rel	Jump on accumulator = 0	2		2	60

		JNZ rel	Jump on accumulator ¹ 0	2		2	70

		CJNE A,dir,rel	Compare A,direct jne relative	3		2	B5

		CJNE A,#d,rel	Compare A,immediate jne relative	3		2	B4

		CJNE Rn,#d,rel	Compare register, immediate jne relative	3		2	B8-BF

		CJNE @Ri,#d,rel	Compare indirect, immediate jne relative	3		2	B6-B7

		DJNZ Rn,rel	Decrement register, jnz relative	2		2	D8-DF

		DJNZ dir,rel	Decrement direct byte, jnz relative	3		2	D5


			MISCELLANEOUS

		NOP	No operation	1		1	00

2003 Dec 8

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonCPU Block Diagram P89LPC906KB Code Flash Oscillator DividerByte Data RAM Block Diagram P89LPC907Uart ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData CodeCPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator OptionExternal Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm RegisterMed freq LOW Power Select P89LPC906High freq Low freqCPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt ArbitrationSummary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RIBopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RSTOpen Drain Output Configuration Port latch dataPort 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm CclkUndefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesUpdating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTsFraming Error Break DetectBrgcon Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control registerPrescaler Power Down OperationWatchdog Clock Source CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, aGeneral Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Address xxxxh User Security BytesSECx Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingD8-DF RetiB8-BF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908