Philips P89LPC907, P89LPC906, P89LPC908 user manual Scon

Page 62

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

UART

P89LPC906/907/908

 

.

SCON

Address: 98h Bit addressable

Reset Source(s): Any reset

Reset Value: 00000000B

7

6

5

4

3

2

1

0

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

SCON.7

SM0/FE

The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit

 

 

is read and written as SM0, which with SM1, defines the serial port mode. If SMOD0 = 1,

 

 

this bit is read and written as FE (Framing Error). FE is set by the receiver when an invalid

 

 

stop bit is detected. Once set, this bit cannot be cleared by valid frames but is cleared by

 

 

software. (Note: UART mode bits SM0 and SM1 should be programmed when SMOD0 is

 

 

’0’ - default mode on any reset.)

SCON. 6

SM1

With SM0, defines the serial port mode (see table below).

 

SM0, SM1

UART Mode

UART 0 Baud Rate

 

0 0

0: shift register

CCLK/16 (default mode on any reset)

 

0 1

1: 8-bit UART

Variable (see Table )

 

1 0

2: 9-bit UART

CCLK/32 or CCLK/16

 

1 1

3: 9-bit UART

Variable (see Table )

SCON.5

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if

 

 

SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode

 

 

0, SM2 should be 0. In Mode 1, SM2 must be 0.

SCON.4

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable

 

 

reception.

 

SCON.3

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as

 

 

desired.

 

SCON.2

RB8

The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0), RB8 is

 

 

the stop bit that was received. In Mode 0, RB8 is undefined.

SCON.1

TI

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the

 

 

the stop bit (see description of INTLO bit in SSTAT register) in the other modes. Must be

 

 

cleared by software.

SCON.0

RI

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or

 

 

approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3, if

SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is set near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be cleared by software.

Figure 8-3: Serial Port Control Register (SCON)

2003 Dec 8

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonCPU Block Diagram P89LPC906KB Code Flash Oscillator DividerByte Data RAM Block Diagram P89LPC907Uart ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData CodeCPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator OptionExternal Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm RegisterMed freq LOW Power Select P89LPC906High freq Low freqCPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt ArbitrationSummary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RIBopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RSTOpen Drain Output Configuration Port latch dataPort 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFnTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm CclkUndefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVMREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesUpdating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control registerPrescaler Power Down OperationWatchdog Clock Source CLKWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, aGeneral Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 Address xxxxh User Security BytesSECx Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingD8-DF RetiB8-BF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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