Philips P89LPC907, P89LPC906, P89LPC908 user manual Tmod, TMOD.7, TMOD.6, TMOD.3, TMOD.2

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Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

TIMERS 0 AND 1

P89LPC906/907/908

5. TIMERS 0 AND 1

 

 

The P89LPC906/907/908 has two general-purpose counter/timers which are similar to the 80C51 Timer 0 and Timer 1. Timer 0 of the P89LPC907 can be configured to operate either as a timer or event counter (see Figure 5-1). An option to automatically toggle the T0 pin upon timer overflow has been added. Timer 1 of the P89LPC907 and both Timer 0 and Timer 1 of the P89LPC906 and P89LPC908 devices may only function as timers.

In the “Timer” function, the timer is incremented every PCLK.

In the “Counter” function, the Timer 0 register is incremented in response to a 1-to-0 transition on the external input pin, T0, which is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (4 CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is 1/4 of the CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

The “Timer” or “Counter” function is selected by control bit T0C/T in the Special Function Register TMOD. Timer 0 and Timer 1 of the P89LPC906 and P89LPC908, and Timer 1 of the P89LPC907 have four operating modes (modes 0, 1, 2, and 3), which are selected by bit-pairs (TnM1, TnM0) in TMOD. Modes 0, 1, 2 and 3 are the same for both Timers. Mode 3 is different. The operating modes are described later in this section. In addition to these modes, Timer 0 of the P89LPC907 has mode 6. Additionally the T0M2 mode bit in TAMOD is used to specify modes with Timer 0 of the P89LPC907.

TMOD

 

 

 

7

6

5

4

 

3

2

 

 

1

0

 

Address: 89h

 

 

 

 

 

 

 

 

 

 

 

-

-

T1M1

T1M0

 

-

T0C/T

 

 

T0M1

T0M0

 

Not bit addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Source(s): Any source

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value:

00000000B

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

TMOD.7

-

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

TMOD.6

-

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

TMOD.5, 4

T1M1,T1M0

Mode Select for Timer 1. These bits are used to determine the Timer 1 mode (see Figure

 

 

 

 

5-2).

 

 

 

 

 

 

 

 

 

 

 

TMOD.3

-

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

TMOD.2

T0C/T

 

 

Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from CCLK). Set

 

 

 

 

 

for Counter operation (input from T0 input pin).P89LPC907. When writing to this register

 

 

 

 

on the P89LPC906 or P89LPC908 devices, this bit position should be written with a zero.

TMOD.1, 0

T0M1,T0M0

Mode Select for Timer 0. These bits are used to determine the Timer 0 mode (see Figure

 

 

 

 

5-2). On the P89LPC907 these bits are used with the T0M2 bit in the TAMOD register to

 

 

 

 

determine the Timer 0 mode (see Figure 5-2).

 

 

 

 

 

 

 

Figure 5-1: Timer/Counter Mode Control register (TMOD)

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsKB Code Flash Block Diagram P89LPC906CPU Oscillator DividerUart Block Diagram P89LPC907Byte Data RAM ClockData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxDSpecial function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR CodeClock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionBIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterHigh freq LOW Power Select P89LPC906Med freq Low freqCPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RSTPort latch data Open Drain Output ConfigurationPUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFnTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm CclkWDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVMREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartBaud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesPrescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control registerWatchdog Clock Source Power Down OperationPrescaler CLKWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, aUsing Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 SECx User Security BytesAddress xxxxh Unprogrammed value 00hBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanB8-BF RetiD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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