Philips P89LPC907, P89LPC906, P89LPC908 user manual Accessing Additional Flash Elements

Page 92

Philips Semiconductors

 

User’s Manual - Preliminary -

 

 

 

 

 

FLASH PROGRAM MEMORY

P89LPC906/907/908

 

 

 

Figure 14-2: Assembly language routine to erase/program all or part of a page

 

 

 

 

 

 

 

unsigned

char idata dbytes[16];

 

// data buffer

 

unsigned

char Fm_stat;

// status result

bit PGM_USER (unsigned char, unsigned char); bit prog_fail;

void main ()

{

prog_fail=PGM_USER(0x1F,0xC0);

}

bit PGM_USER (unsigned char page_hi, unsigned char page_lo)

{

 

#define LOAD

0x00

// clear page register, enable loading

 

#define EP

0x68

// erase & program page

 

unsigned char

i;

// loop count

FMCON

=

LOAD;

//

//load command, clears page reg

FMADRH = page_hi;

 

FMADRL = page_lo;

//write my page address to addr regs

for

(i=0;i<16;i=i+1)

 

 

 

{

FMDATA = dbytes[i];

 

}

FMCON

EP;

//erase & prog page command

=

Fm_stat

= FMCON;

 

//read the result status

if ((Fm_stat & 0x0F)!=0) prog_fail=1; else prog_fail=0; return(prog_fail);

}

Figure 14-3: C-language routine to erase/program all or part of a page

ACCESSING ADDITIONAL FLASH ELEMENTS

In addition to the user code array, the user’s firmware may access additional flash elements. These include UCFG1, the Boot Vector, Status Bit, and signature bytes. Access of these elements uses a slightly different method than that used to access the user code memory. Signature bytes are read-only. Security bytes may be erased only under certain conditions.

IAP-Lite is performed in the application under the control of the microcontroller’s firmware using four SFRs to facilitate erasing, programming, or reading. These SFRs are:

•FMCON (Flash Control Register). When read, this is the status register. When written, this is a command register. Note that the status bits are cleared to ’0’s when the command is written.

•FMDATA (Flash Data Register). Accepts data to be loaded into or from the flash element.

•FMADRL (Flash memory address low). Used to specify the flash element.

The flash elements that may be accessed and their addresses are shown in Table 14-1.

2003 Dec 8

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonBlock Diagram P89LPC906 KB Code FlashCPU Oscillator DividerBlock Diagram P89LPC907 UartByte Data RAM ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR CodeEnhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionCPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterLOW Power Select P89LPC906 High freqMed freq Low freqCPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Port latch dataINPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFnTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm CclkRC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVMREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesSFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control registerPower Down Operation Watchdog Clock SourcePrescaler CLKWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, aFeatures Using Flash AS Data StorageGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 User Security Bytes SECxAddress xxxxh Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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