Philips P89LPC907, P89LPC906 Port Configurations, QUASI-BIDIRECTIONAL Output Configuration, Rst

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Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

I/O PORTS

P89LPC906/907/908

4. I/O PORTS

 

 

The P89LPC906/907/908 has between 3 and 6 I/O pins. The exact number of I/O pins available depends on the clock and reset options chosen:

Table 4-1: Number of I/O Pins Available

 

 

 

 

Number of I/O

Clock Source

Reset Option

Pins

 

 

 

 

8-Pin Package

On-chip oscillator or watchdog

No external reset(except during power-up)

6

oscillator

External

 

pin supported

5

RST

External clock input

No external reset(except during power-up)

5

(P89LPC906)

External

 

pin supported

4

RST

Low/medium/high speed oscillator

No external reset(except during power-up)

4

(external crystal or resonator)

 

 

 

 

 

 

 

 

External RST pin supported

3

(P89LPC906)

 

 

 

 

 

 

 

 

 

PORT CONFIGURATIONS

All but one I/O port pin on the P89LPC906/907/908 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 4-2. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured.

Table 4-2: Port Output Configuration Settings

PxM1.y

PxM2.y

Port Output Mode

0

0

Quasi-bidirectional

 

 

 

0

1

Push-Pull

 

 

 

1

0

Input Only (High Impedance)

 

 

 

1

1

Open Drain

 

 

 

QUASI-BIDIRECTIONAL OUTPUT CONFIGURATION

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pullup transistors in the quasi-bidirectional output that serve different purposes.

One of these pullups, called the "very weak" pullup, is turned on whenever the port latch for the pin contains a logic 1. This very weak pullup sources a very small current that will pull the pin high if it is left floating.

A second pullup, called the "weak" pullup, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pullup provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, this weak pullup turns off, and only the very weak pullup remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pullup and pull the port pin below its input threshold voltage.

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsBrgcon Framing ErrorBreak Detect Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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