Philips P89LPC908, P89LPC907 user manual PIN Descriptions P89LPC906

Page 12

Philips Semiconductors

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

GENERAL DESCRIPTION

P89LPC906/907/908

PIN DESCRIPTIONS - P89LPC906

 

 

 

 

 

 

 

 

 

Mnemonic

Pin no.

Type

Name and function

 

 

P0.4 - P0.6

3, 7,8

I/O

Port 0:

Port 0 is an I/O port with a user-configurable output types. During reset Port

 

 

 

 

0 latches are configured in the input only mode with the internal pullup

 

 

 

 

disabled. The operation of port 0 pins as inputs and outputs depends upon

 

 

 

 

the port configuration selected. Each port pin is configured independently.

 

 

 

 

Refer to the section Port Configurations on page 35 and the DC Electrical

 

 

 

 

Characteristics in the datasheet for details.

 

 

 

 

 

The Keypad Interrupt feature operates with port 0 pins.

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

Port 0 also provides various special functions as described below.

 

8

I/O

P0.4

Port 0 bit 4.

 

 

 

 

I

CIN1A

Comparator 1 positive input.

 

 

 

 

I

KBI4

Keyboard Input 4.

 

 

 

7

I/O

P0.5

Port 0 bit 5.

 

 

 

 

I

CMPREFComparator reference (negative) input.

 

 

 

 

I

KBI5

Keyboard Input 5.

 

 

 

3

I/O

P0.6

Port 0 bit 6.

 

 

 

 

O

CMP1

Comparator 1 output.

 

 

 

 

I

KBI6

Keyboard Input 6.

 

 

P1.5

1

I

P1.5

Port 1 bit 5. (Input only)

 

 

 

 

I

RST

External Reset input during power-on or if selected via UCFG1. When

 

 

 

 

functioning as a reset input a low on this pin resets the microcontroller,

 

 

 

 

causing I/O ports and peripherals to take on their default states, and the

 

 

 

 

processor begins execution at address 0. Also used during a power-on

 

 

 

 

sequence to force In-Circuit Programming mode.

P3.0 - P3.1

4,5

I/O

Port 3

Port 3 is an I/O port with a user-configurable output types. During reset Port

 

 

 

 

3 latches are configured in the input only mode with the internal pullups

 

 

 

 

disabled. The operation of port 3 pins as inputs and outputs depends upon

 

 

 

 

the port configuration selected. Each port pin is configured independently.

 

 

 

 

Refer to the section Port Configurations on page 35 and the DC Electrical

 

 

 

 

Characteristics in the datasheet for details.

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

Port 3 also provides various special functions as described below:

 

5

I/O

P3.0

Port 3 bit 0.

 

 

 

 

O

XTAL2 Output from the oscillator amplifier (when a crystal oscillator option is

 

 

 

 

selected via the FLASH configuration).

 

 

 

 

O

CLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can

 

 

 

 

be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

 

 

 

 

external clock input, except when XTAL1/XTAL2 are used to generate clock

 

 

 

 

source for the Real-Time clock/system timer.

 

 

 

4

I/O

P3.1

Port 3 bit 1.

 

 

 

 

I

XTAL1

Input to the oscillator circuit and internal clock generator circuits (when

 

 

 

 

selected via the FLASH configuration). It can be a port pin if internal RC

 

 

 

 

oscillator or watchdog oscillator is used as the CPU clock source, AND if

 

 

 

 

XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/

 

 

 

 

system timer.

 

 

VSS

2

I

Ground: 0V reference.

 

 

VDD

6

I

Power Supply: This is the power supply voltage for normal operation as well as Idle and

 

 

 

Power down modes.

 

 

2003 Dec 8

12

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonBlock Diagram P89LPC906 KB Code FlashCPU Oscillator DividerBlock Diagram P89LPC907 UartByte Data RAM ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR CodeEnhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionCPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterLOW Power Select P89LPC906 High freqMed freq Low freqCPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Port latch dataINPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm CclkRC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesSFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsFraming Error Break DetectBrgcon Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control registerPower Down Operation Watchdog Clock SourcePrescaler CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, aFeatures Using Flash AS Data StorageGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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