Philips P89LPC908, P89LPC906, P89LPC907 user manual Power Reduction Modes

Page 55

Philips Semiconductors

 

User’s Manual - Preliminary -

 

 

 

POWER MONITORING FUNCTIONS

P89LPC906/907/908

Table 7-2: Power Reduction Modes

 

 

PMOD1

PMOD0

Description

 

 

(PCON.1)

(PCON.0)

 

 

 

 

 

0

0

Normal Mode (Default) - no power reduction.

 

 

 

 

 

0

1

Idle Mode. The Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

 

 

 

 

Power down mode:

 

 

 

 

The Power down mode stops the oscillator in order to minimize power consumption.

 

 

The P89LPC906/907/908 exits Power down mode via any reset, or certain interrupts - brownout

 

 

Interrupt, keyboard, Real-time clock (system timer), watchdog, and comparator trips. Waking up by reset

 

 

is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the

 

 

corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set.

 

 

 

 

In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been

 

 

selected as the system clock AND the RTC is enabled

 

 

 

 

In Power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM.

 

 

This retains the RAM contents at the point where Power down mode was entered. SFR contents are not

 

 

guaranteed after VDD has been lowered to VRAM, therefore it is recommended to wake up the processor

1

0

via Reset in this situation. VDD must be raised to within the operating range before the Power down mode

is exited.

 

 

 

 

When the processor wakes up from Power down mode, it will start the oscillator immediately and begin

 

 

execution when the oscillator is stable. Oscillator stability is determined by counting 1024 CPU clocks

 

 

after start-up when one of the crystal oscillator configurations is used, or 256 clocks after start-up for the

 

 

internal RC or external clock input configurations.

 

 

 

 

Some chip functions continue to operate and draw power during Power down mode, increasing the total

 

 

power used during Power down. These include:

 

 

•Brownout Detect

•Watchdog Timer if WDCLK (WDCON.0) is ’1’.

•Comparator (Note: Comparator can be powered down separately with PCONA.5 set to ’1’ and comparator disabled);

•Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless RTCPD, i.e., PCONA.7 is ’1’).

 

 

Total Power down mode: This is the same as Power down mode except that the Brownout Detection

 

 

circuitry and the voltage comparators are also disabled to conserve additional power. Note that a

 

 

brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout interrupt cannot

 

 

be used as a wakeup source.The internal RC oscillator is disabled unless both the RC oscillator has

 

 

been selected as the system clock AND the RTC is enabled.

 

 

The following are the wakeup options supported:

1

1

• Watchdog Timer if WDCLK (WDCON.0) is ’1’. Could generate Interrupt or Reset, either one can wake

 

 

up the device

•Keyboard Interrupt

•Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless RTCPD, i.e., PCONA.7 is ’1’).

•Note: Using the internal RC-oscillator to clock the RTC during Power down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock is running during Power down.

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsBreak Detect Framing ErrorBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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