Philips P89LPC908 Port Output Configuration P89LPC906, Port Output Configuration P89LPC907

Page 38

Philips Semiconductors

 

 

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

 

 

 

 

 

 

I/O PORTS

 

 

 

 

P89LPC906/907/908

Table 4-3: Port Output Configuration - P89LPC906

 

 

 

 

 

 

Port

Configuration SFR Bits

Alternate Usage

Notes

 

 

 

Pin

PxM1.y

PxM2.y

 

 

 

 

 

 

 

 

 

 

 

 

P0.4

P0M1.4

P0M2.4

KBI4,CIN1A

Refer to section "Port 0 Analog Functions" for usage as

 

 

 

 

 

 

 

 

 

 

 

P0.5

P0M1.5

P0M2.5

KBI5,CMPREF

analog inputs CIN1A and CMPREF.

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.6

P0M1.6

P0M2.6

KBI6,CMP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input only. Usage as general purpose input or

 

is

 

 

 

 

 

 

 

 

RST

 

P1.5

not configurable

 

RST

 

determined by User Configuration Bit RPD (UCFG1.6).

 

 

 

 

 

 

 

 

Always a reset input during a power-on sequence.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.0

P3M1.0

P3M2.0

XTAL2,CLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.1

P3M1.1

P3M2.1

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4-4: Port Output Configuration - P89LPC907

 

 

 

 

 

 

Port

Configuration SFR Bits

Alternate Usage

Notes

 

 

 

Pin

PxM1.y

PxM2.y

 

 

 

 

 

 

 

 

 

 

 

 

P0.4

P0M1.4

P0M2.4

KBI4,CIN1A

Refer to section "Port 0 Analog Functions" for usage as

 

 

 

 

 

 

 

 

 

 

 

P0.5

P0M1.5

P0M2.5

KBI5,CMPREF

analog inputs CIN1A and CMPREF.

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.6

P0M1.6

P0M2.6

KBI6,CMP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0

P1M1.0

P1M2.0

 

TxD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.2

P1M1.2

P1M2.2

 

T0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input only. Usage as general purpose input or

 

is

 

 

P1.5

not configurable

 

 

 

RST

 

 

RST

 

determined by User Configuration Bit RPD (UCFG1.6).

 

 

 

 

 

 

 

 

Always a reset input during a power-on sequence.

 

 

 

 

 

 

 

 

 

 

Table 4-5: Port Output Configuration - P89LPC908

 

 

 

 

 

 

Port

Configuration SFR Bits

Alternate Usage

Notes

 

 

 

Pin

PxM1.y

PxM2.y

 

 

 

 

 

 

 

 

 

 

 

 

P0.4

P0M1.4

P0M2.4

KBI4,CIN1A

Refer to section "Port 0 Analog Functions" for usage as

 

 

 

 

 

 

 

 

 

 

 

P0.5

P0M1.5

P0M2.5

KBI5,CMPREF

analog inputs CIN1A and CMPREF.

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.6

P0M1.6

P0M2.6

KBI6,CMP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0

P1M1.0

P1M2.0

 

TxD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.1

P1M1.1

P1M2.1

 

RxD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input only. Usage as general purpose input or

 

is

 

 

P1.5

not configurable

 

 

 

RST

 

 

RST

 

determined by User Configuration Bit RPD (UCFG1.6).

 

 

 

 

 

 

 

 

Always a reset input during a power-on sequence.

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4-6: Additional Port Features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

•After power-up, all I/O pins except P1.5, may be configured by software.

•Pin P1.5 is input only.

•Every output on the P89LPC906/907/908 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC906/907/908 datasheet for detailed specifications.

2003 Dec 8

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonCPU Block Diagram P89LPC906KB Code Flash Oscillator DividerByte Data RAM Block Diagram P89LPC907Uart ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData CodeCPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator OptionExternal Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm RegisterMed freq LOW Power Select P89LPC906High freq Low freqCPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt ArbitrationSummary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RIBopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RSTOpen Drain Output Configuration Port latch dataPort 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFnTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm CclkUndefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVMREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesUpdating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control registerPrescaler Power Down OperationWatchdog Clock Source CLKWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, aGeneral Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 Address xxxxh User Security BytesSECx Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingD8-DF RetiB8-BF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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