Philips P89LPC906, P89LPC908, P89LPC907 user manual Flash Program Memory

Page 90

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

FLASH PROGRAM MEMORY

P89LPC906/907/908

 

"wrap -around" to the first byte in the page register, but will not affect FMADRL[7:4]. Bytes loaded into the page register do not have to be continuous. Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writ- ing to FMDATA. However, each location in the page register can only be written once following each LOAD command. Attempts to write to a page register location more than once should be avoided.

FMADRH and FMADRL[7:4] are used to select a page of code memory for the erase-program function. When the erase-pro- gram command is written to FMCON, the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register. Only the bytes that were loaded into the page register will be erased and programmed in the user code array. Other bytes within the user code memory will not be affected.

Writing the erase-program command (68H) to FMCON will start the erase-program process and place the CPU in a program- idle state. The CPU will remain in this idle state until the erase-program cycle is either completed or terminated by an interrupt. When the program-idle state is exited, FMCON will contain status information for the cycle.

If an interrupt occurs during an erase/programming cycle, the erase/programming cycle will be aborted and the OI flag (Opera- tion Interrupted) in FMCON will be set. If the application permits interrupts during erasing-programming, the user code should check the OI flag (FMCON.0) after each erase-programming operation to see if the operation was aborted. If the operation was aborted, the user’s code will need to repeat the process starting with loading the page register.

The erase-program cycle takes 4ms to complete, regardless of the number of bytes that were loaded into the page register.

Erasing-programming of a single byte (or multiple bytes) in code memory is accomplished using the following steps:

•Write the LOAD command (00H) to FMCON. The LOAD command will clear all locations in the page register and their corresponding update flags.

•Write the address within the page register to FMADRL. Since the loading the page register uses FMADRL[5:0], and since the erase-program command uses FMADRH and FMADRL[7:4], the user can write the byte location within the page register (FMADRL[3:0]) and the code memory page address (FMADRH and FMADRL[7:4]) at this time.

•Write the data to be programmed to FMDATA. This will increment FMADRL pointing to the next byte in the page register.

•Write the address of the next byte to be programmed to FMADRL, if desired. (Not needed for contiguous bytes since FMADRL is auto-incremented). All bytes to be programmed must be within the same page.

•Write the data for the next byte to be programmed to FMDATA.

•Repeat writing of FMADRL and/or FMDATA until all desired bytes have been loaded into the page register.

•Write the page address in user code memory to FMADRH and FMADRL[7:4], if not previously included when writing the page register address to FMADRL[3:0].

•Write the erase-program command (68H) to FMCON,starting the erase-program cycle.

•Read FMCON to check status. If aborted, repeat starting with the LOAD command.

An assembly language routine to load the page register and perform an erase/program operation is shown in Figure 14-2. A similar C-language routine is shown in Figure 14-3.

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonCPU Block Diagram P89LPC906KB Code Flash Oscillator DividerByte Data RAM Block Diagram P89LPC907Uart ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 TxD PIN Descriptions P89LPC907P1.0 P1.2P1.1 PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 SFR Memory OrganizationData CodeCPU Clock Oscclk Enhanced CPUClock Definitions LOW Speed Oscillator Option P89LPC906ON-CHIP RC Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 Watchdog Oscillator OptionExternal Clock Input Option P89LPC906 CPU Clock Cclk Wakeup DelayBIT Symbol Function CPU Clock Cclk Modification Divm RegisterMed freq LOW Power Select P89LPC906High freq Low freqCPU Clocks Summary of Interrupts P89LPC906 Description Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Interrupt ArbitrationSummary of Interrupts P89LPC907,P89LPC908 Description External Interrupt InputsExternal Interrupt PIN Glitch Suppression TI & RIBopd EBO Rtcf Kbif Interrupts Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration RSTOpen Drain Output Configuration Port latch dataPort 0 Analog Functions INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.6 TmodTMOD.7 TMOD.3Tamod P89LPC907 Overflows. ModeMode TAMOD.7-1Tcon T0C/T = Overflow PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Xclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Divm CclkUndefined RC Oscillator/DIVMWDT Oscillator/DIVM External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesUpdating the BRGR1 and BRGR0 Sfrs SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTsFraming Error Break DetectBrgcon Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled More about Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator Interrupt Comparator and Power Reduction ModesInternal Reference Voltage CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Watchdog Timer in Timer ModePrescaler Reset Pclk Control registerPrescaler Power Down OperationWatchdog Clock Source CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVX@DPTR, aGeneral Description FeaturesUsing Flash AS Data Storage Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Address xxxxh User Security BytesSECx Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingD8-DF RetiB8-BF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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