Philips P89LPC908, P89LPC906, P89LPC907 user manual CMP1 Cmpref

Page 19

Philips Semiconductors

 

 

 

 

 

 

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL DESCRIPTION

 

 

 

 

 

 

P89LPC906/907/908

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

Description

SFR

 

 

 

Bit Functions and Addresses

 

 

Reset Value

 

Address

MSB

 

 

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

 

 

KBMASK#

Keypad Interrupt Mask Register

86H

 

 

 

 

 

 

 

 

 

 

00H

00000000

 

KBPATN#

Keypad Pattern Register

93H

 

 

 

 

 

 

 

 

 

 

FFH

11111111

 

 

 

 

87

86

85

 

84

83

82

81

80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0*

Port 0

80H

-

CMP1/

CMPREF/

CIN1A/

-

KB2

-

KB0

Note 1

 

KB6

 

KB5

KB4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

97

96

95

 

94

93

92

91

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1*

Port 1

90H

-

-

 

 

 

-

-

T0

-

TxD

 

 

 

 

RST

 

 

 

 

 

 

 

B7

B6

 

B5

B4

B3

B2

B1

B0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0M1#

Port 0 Output Mode 1

84H

-

(P0M1.6)

(P0M1.5)

(P0M1.4)

-

(P0M1.2)

-

(P0M1.0)

FFH

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0M2#

Port 0 Output Mode 2

85H

-

(P0M2.6)

(P0M2.5)

(P0M2.4)

-

(P0M2.2)

-

(P0M2.0)

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

FFH1

11111111

 

P1M1#

Port 1 Output Mode 1

91H

-

-

(P1M1.5)

-

-

(P1M1.2)

-

(P1M1.0)

 

P1M2#

Port 1 Output Mode 2

92H

-

-

(P1M2.5)

-

-

(P1M2.2)

-

(P1M2.0)

00H1

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON#

Power Control Register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00000000

 

PCONA#

Power Control Register A

B5H

RTCPD

 

VCPD

 

 

-

SPD

 

 

 

 

 

D7

D6

 

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW*

Program Status Word

D0H

CY

AC

 

F0

RS1

RS0

OV

F1

P

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PT0AD#

Port 0 Digital Input Disable

F6H

-

-

PT0AD.5

PT0AD.4

-

-

-

-

00H

xx00000x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RSTSRC#

Reset Source Register

DFH

-

-

BOF

POF

-

R_WD

R_SF

R_EX

Note 2

 

 

 

 

 

 

 

 

 

 

 

 

60H1,5

011xxx00

 

 

 

 

 

 

 

 

 

 

 

 

 

RTCCON#

Real-Time Clock Control

D1H

RTCF

RTCS1

RTCS0

-

-

-

ERTC

RTCEN

 

RTCH#

Real-Time Clock Register High

D2H

 

 

 

 

 

 

 

 

 

 

00H5

00000000

 

 

 

 

 

 

 

 

 

 

 

 

RTCL#

Real-Time Clock Register Low

D3H

 

 

 

 

 

 

 

 

 

 

00H5

00000000

 

SBUF

Serial Port Data Buffer Register

99H

 

 

 

 

 

 

 

 

 

 

xxH

xxxxxxxx

 

 

 

 

9F

9E

 

9D

9C

9B

9A

99

98

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCON*

Serial Port Control

98H

SM0

SM1

SM2

-

TB8

-

TI

-

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTAT#

Serial Port Extended Status Register

BAH

DBMOD

INTLO

CIDIS

DBISEL

-

-

-

-

00H

00000000

 

SP

Stack Pointer

81H

 

 

 

 

 

 

 

 

 

 

07H

00000111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAMOD#

Timer 0 Auxiliary Mode

8FH

-

-

-

 

-

-

-

-

T0M2

00H

xxx0xxx0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8F

8E

 

8D

8C

8B

8A

89

88

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCON*

Timer 0 and 1 Control

88H

TF1

TR1

 

TF0

TR0

-

-

-

-

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2003 Dec 8

19

Page 18 Page 20
Image 19
Page 18 Page 20
Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsBreak Detect Framing ErrorBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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