Philips P89LPC907, P89LPC906, P89LPC908 user manual Feed Sequence

Page 80

Philips Semiconductors

 

 

 

 

 

 

 

 

User’s Manual - Preliminary -

WATCHDOG TIMER

 

 

 

 

 

P89LPC906/907/908

Watchdog

 

 

 

 

 

 

 

 

 

Oscillator

÷32

÷2

÷2

 

÷2

÷2

÷2

÷2

÷2

 

PCLK

 

 

 

 

 

 

 

 

 

 

 

÷32

÷64

÷128

÷256

÷512

÷1024

÷2048

 

÷4096

 

WDCLK after a

 

 

 

 

 

 

 

 

 

 

watchdog feed

 

 

 

 

 

 

 

 

 

 

sequence

 

 

 

 

 

 

 

 

TO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WATCHDOG

 

 

000

 

 

 

 

 

 

 

DOWN

 

 

 

 

 

 

 

 

 

COUNTER

 

 

001

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(after one

 

 

010

 

 

 

 

 

 

 

PRE2

 

 

 

 

 

 

 

 

prescaler

 

011

 

 

 

 

 

 

 

 

DECODE

 

 

 

 

 

 

 

count delay

PRE1

100

 

 

 

 

 

 

 

 

 

101

 

 

 

 

 

 

 

 

PRE0

 

110

 

 

 

 

 

 

 

 

 

111

 

 

 

 

 

 

 

 

Figure 12-1: Watchdog Prescaler

FEED SEQUENCE

The watchdog timer control register and the 8-bit down counter (Figure 12-3) are not directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control register and the 8-bit down counter. Before the feed sequence, any new values written to these two SFRs will not take effect. To avoid a watchdog reset, the watchdog timer needs to be fed (via a special sequence of software action called the feed sequence) prior to reaching an underflow.

To feed the watchdog, two write instructions must be sequentially executed successfully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register. An incorrect feed sequence will cause an immediate watchdog reset. The program sequence to feed the watchdog timer is as follows:

CLR

EA

; disable interrupt

MOV

WFEED1,#0A5h

; do watchdog feed part 1

MOV

WFEED2,#05Ah

; do watchdog feed part 2

SETB

EA

; enable interrupt

This sequence assumes that the P89LPC906/907/908 interrupt system is enabled and there is a possibility of an interrupt request occuring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset. If it is known that no interrupt could occur during the feed sequence, the instructions to disable and re-enable interrupts may be removed.

In watchdog mode (WDTE = 1), writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8-bit down counter, and the WDCON to the shadow register. If writing to the WDCON register is not immediately followed by the feed sequence, a watchdog reset will occur.

For example: setting WDRUN = 1:

MOV

ACC,WDCON

; get WDCON

SETB

ACC.2

; set WD_RUN=1

MOV

WDL,#0FFh

; New count to be loaded to 8-bit down counter

CLR

EA

; disable interrupt

MOV

WDCON,ACC

; write back to WDCON (after the watchdog is enabled, a feed must occur

 

 

; immediately)

2003 Dec 8

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Page 79 Page 81
Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonBlock Diagram P89LPC906 KB Code FlashCPU Oscillator DividerBlock Diagram P89LPC907 UartByte Data RAM ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR CodeEnhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionCPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterLOW Power Select P89LPC906 High freqMed freq Low freqCPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Port latch dataINPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC908 Port Output Configuration P89LPC906Port Output Configuration P89LPC907 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFnTR0 ENT0 Pclk TH0 Timer Overflow Toggle Output P89LPC907Pclk TL0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm CclkRC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVMREAL-TIME Clock INTERRUPT/WAKE UP Reset Sources Affecting the REAL-TIME ClockChanging RTCS1-0 Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Brownout Options POWER-ON DetectionPower Reduction Modes Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesSFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control registerPower Down Operation Watchdog Clock SourcePrescaler CLKWatchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, aFeatures Using Flash AS Data StorageGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aUCFG1 ERASE-PROGRAMMING Additional Flash ElementsReading Additional Flash Elements Fmadrl Conf P89LPC906 User Configuration BytesUCFG1 User Security Bytes SECxAddress xxxxh Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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