Philips P89LPC906, P89LPC907 user manual Special function registers table P89LPC908

Page 21

Philips Semiconductors

 

 

 

 

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL DESCRIPTION

 

 

 

 

P89LPC906/907/908

 

Table 3: Special function registers table - P89LPC908

 

 

 

 

 

 

 

 

 

 

Name

Description

SFR

 

 

Bit Functions and Addresses

 

 

Reset Value

 

Address

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

 

 

 

E7

E6

E5

E4

E3

E2

E1

E0

 

 

 

 

ACC*

Accumulator

E0H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AUXR1#

Auxiliary Function Register

A2H

-

EBRR

-

-

SRST

0

-

DPS

000000x0

 

 

 

 

F7

F6

F5

F4

F3

F2

F1

F0

 

 

 

 

B*

B Register

F0H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

BRGR0#§

Baud Rate Generator Rate Low

BEH

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

BRGR1#§

Baud Rate Generator Rate High

BFH

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRGCON#

Baud Rate Generator Control

BDH

-

-

-

-

-

-

SBRGS

BRGEN

00H

xxxxxx00

 

 

 

 

 

 

 

 

 

 

 

 

00H1

xx000000

 

 

 

 

 

 

 

 

 

 

 

 

 

CMP1#

Comparator 1 Control Register

ACH

-

-

CE1

-

CN1

OE1

CO1

CMF1

 

DIVM#

CPU Clock Divide-by-M Control

95H

 

 

 

 

 

 

 

 

00H

00000000

 

DPTR

Data Pointer (2 bytes)

 

 

 

 

 

 

 

 

 

 

 

 

 

DPH

Data Pointer High

83H

 

 

 

 

 

 

 

 

00H

00000000

 

DPL

Data Pointer Low

82H

 

 

 

 

 

 

 

 

00H

00000000

 

FMADRH#

Program Flash Address High

E7H

 

 

 

 

 

 

 

 

00H

00000000

 

FMADRL#

Program Flash Address Low

E6H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Flash Control (Read)

 

BUSY

-

-

-

HVA

HVE

SV

OI

70H

01110000

 

FMCON#

 

E4H

 

 

 

 

 

 

 

 

 

 

 

 

Program Flash Control (Write)

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

FMDATA#

Program Flash Data

E5H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IEN0*

Interrupt Enable 0

A8H

EA

EWDRT

EBO

ES/ESR

ET1

-

ET0

-

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EF

EE

ED

EC

EB

EA

E9

E8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00x00000

 

IEN1*#

Interrupt Enable 1

E8H

-

EST

-

-

-

EC

EKBI

-

 

 

 

 

BF

BE

BD

BC

BB

BA

B9

B8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

x0000000

 

IP0*

Interrupt Priority 0

B8H

-

PWDRT

PBO

PS/PSR

PT1

-

PT0

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IP0H#

Interrupt Priority 0 High

B7H

-

PWDRT

PBOH

PSH/

PT1H

-

PT0H

-

00H1

x0000000

 

 

 

 

 

H

 

PSRH

 

 

 

 

 

 

 

 

 

 

 

FF

FE

FD

FC

FB

FA

F9

F8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00x00000

 

IP1*#

Interrupt Priority 1

F8H

-

PST

-

-

-

PC

PKBI

-

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00x00000

 

IP1H#

Interrupt Priority 1 High

F7H

-

PSTH

-

-

-

PCH

PKBIH

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBCON#

Keypad Control Register

94H

-

-

-

-

-

-

PATN_S

KBIF

00H1

xxxxxx00

 

 

 

 

 

 

 

 

 

 

EL

 

 

 

 

 

2003 Dec 8

21

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsKB Code Flash Block Diagram P89LPC906CPU Oscillator DividerUart Block Diagram P89LPC907Byte Data RAM ClockData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxDSpecial function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR CodeClock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionBIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterHigh freq LOW Power Select P89LPC906Med freq Low freqCPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RSTPort latch data Open Drain Output ConfigurationPUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm CclkWDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartBaud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsFraming Error Break DetectBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesPrescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control registerWatchdog Clock Source Power Down OperationPrescaler CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, aUsing Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 SECx User Security BytesAddress xxxxh Unprogrammed value 00hBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanB8-BF RetiD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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