Philips P89LPC908, P89LPC907 user manual Special function registers table P89LPC906

Page 15

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

GENERAL DESCRIPTION

P89LPC906/907/908

Special function registers

 

 

Note: Special function registers (SFRs) accesses are restricted in the following ways:

1.User must NOT attempt to access any SFR locations not defined.

2.Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

3.SFR bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:

-’-’ Unless otherwise specified, MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.

-’0’ MUST be written with ’0’, and will return a ’0’ when read.

-’1’ MUST be written with ’1’, and will return a ’1’ when read.

Table 1: Special function registers table - P89LPC906

Name

Description

SFR

 

 

Bit Functions and Addresses

 

 

Reset Value

Address

 

 

 

 

 

 

 

LSB

 

 

MSB

 

 

 

 

 

 

Hex

Binary

 

 

 

 

 

 

 

 

 

 

 

E7

E6

E5

E4

E3

E2

E1

E0

 

 

ACC*

Accumulator

E0H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

000000x0

 

 

 

 

 

 

 

 

 

 

 

AUXR1#

Auxiliary Function Register

A2H

CLKLP

-

-

ENT0

SRST

0

-

DPS

 

 

 

F7

F6

F5

F4

F3

F2

F1

F0

 

 

B*

B Register

F0H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

xx000000

 

 

 

 

 

 

 

 

 

 

 

CMP1#

Comparator 1Control Register

ACH

-

-

CE1

-

CN1

OE1

CO1

CMF1

DIVM#

CPU Clock Divide-by-M Control

95H

 

 

 

 

 

 

 

 

00H

00000000

DPTR

Data Pointer (2 bytes)

 

 

 

 

 

 

 

 

 

 

 

DPH

Data Pointer High

83H

 

 

 

 

 

 

 

 

00H

00000000

DPL

Data Pointer Low

82H

 

 

 

 

 

 

 

 

00H

00000000

FMADRH#

Program Flash Address High

E7H

 

 

 

 

 

 

 

 

00H

00000000

FMADRL#

Program Flash Address Low

E6H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Flash Control (Read)

 

BUSY

-

-

-

HVA

HVE

SV

OI

70H

01110000

FMCON#

 

E4H

 

 

 

 

 

 

 

 

 

 

Program Flash Control (Write)

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

FMCMD.

 

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

FMDATA#

Program Flash Data

E5H

 

 

 

 

 

 

 

 

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IEN0*

Interrupt Enable 0

A8H

EA

EWDRT

EBO

-

ET1

-

ET0

-

00H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EF

EE

ED

EC

EB

EA

E9

E8

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00x00000

IEN1*#

Interrupt Enable 1

E8H

-

-

-

-

-

EC

EKBI

-

 

 

 

BF

BE

BD

BC

BB

BA

B9

B8

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

x0000000

IP0*

Interrupt Priority 0

B8H

-

PWDRT

PBO

-

PT1

-

PT0

-

 

 

 

 

 

 

 

 

 

 

 

 

 

IP0H#

Interrupt Priority 0 High

B7H

-

PWDRT

PBOH

-

PT1H

-

PT0H

-

00H1

x0000000

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

FF

FE

FD

FC

FB

FA

F9

F8

 

 

 

 

 

 

 

 

 

 

 

 

 

00H1

00x00000

IP1*#

Interrupt Priority 1

F8H

-

-

-

-

-

PC

PKBI

-

2003 Dec 8

15

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsFraming Error Break DetectBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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