Philips P89LPC906, P89LPC908 Power Down Operation, Watchdog Clock Source, Prescaler, Clk

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Philips Semiconductors

 

 

 

 

 

 

User’s Manual - Preliminary -

WATCHDOG TIMER

 

 

 

P89LPC906/907/908

 

 

 

 

 

WDL (C1H)

 

 

MOV WFEED1, #0A5H

 

 

 

 

 

 

 

MOV WFEED2, #05AH

 

 

 

 

 

 

 

Watchdog

 

 

 

 

8-Bit Down

 

 

 

Oscillator

÷32

PRESCALER

 

 

 

 

 

 

Counter

 

 

Interrupt

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

control register

 

 

 

SHADOW

 

 

 

 

 

 

 

REGISTER FOR

 

 

 

 

 

 

 

 

WDCON

 

 

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON(A7H)

Figure 12-4: Watchdog Timer in Timer Mode (WDTE = 0)

POWER DOWN OPERATION

The WDT oscillator will continue to run in power down, consuming approximately 50uA, as long as the WDT oscillator is selected as the clock source for the WDT. Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device (see section "Watchdog Clock Source", below ). Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled.

WATCHDOG CLOCK SOURCE

The watchdog timer system has an on-chip 400KHz oscillator. The watchdog timer can be clocked from either the watchdog oscillator or from PCLK (refer to Figure 12-1) by configuring the WDCLK bit in the Watchdog Control Register WDCON. When the watchdog feature is enabled, the timer must be fed regularly by software in order to prevent it from resetting the CPU.

After changing WDCLK (WDCON.0), switching of the clock source will not immediately take effect. As shown in Figure 12-3, the selection is loaded after a watchdog feed sequence. In addition, due to clock synchronization logic, it can take two old clock cycles before the old clock source is deselected, and then an additional two new clock cycles before the new clock source is selected.

Since the prescaler starts counting immediately after a feed, switching clocks can cause some inaccuracy in the prescaler count. The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles.

Note: When switching clocks, it is important that the old clock source is left enabled for 2 clock cycles after the feed completes. Otherwise, the watchdog may become disabled when the old clock source is disabled. For example, suppose PCLK (WCLK=0) is the current clock source. After WCLK is set to ’1’, the program should wait at least two PCLK cycles (4 CCLKs) after the feed completes before going into Power down mode. Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first.

2003 Dec 8

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Contents User Manual Table of Contents Brownout Detection Power-On Detection Power Reduction Modes Power-On reset code execution103 List of Figures List of Figures PIN Configurations P89LPC906Logic Symbols Product ComparisonBlock Diagram P89LPC906 KB Code FlashCPU Oscillator DividerBlock Diagram P89LPC907 UartByte Data RAM ClockBlock Diagram P89LPC908 Data RAM PortPIN Descriptions P89LPC906 PIN Descriptions P89LPC907 P1.0TxD P1.2PIN Descriptions P89LPC908 Keyboard Input P1.0 P1.5P1.1 RxDSpecial function registers Special function registers table P89LPC906MSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Memory Organization DataSFR CodeEnhanced CPU Clock DefinitionsCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Oscillator Option SELECTION- P89LPC906 Clock Output P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionCPU Clock Cclk Wakeup Delay BIT Symbol FunctionExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterLOW Power Select P89LPC906 High freqMed freq Low freqCPU Clocks Flag Bits Address Enable Bits Priority Ranking Interrupt Priority StructureSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt Inputs External Interrupt PIN Glitch SuppressionSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts Port Configurations QUASI-BIDIRECTIONAL Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Port latch dataINPUT-ONLY Configuration PUSH-PULL Output ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Overflows. Mode ModeTamod P89LPC907 TAMOD.7-1Tcon Pclk T0C/T = Overflow TLn THn TFn Interrupt T0 PinT0C/T = Overflow THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyXclk Divm CclkRC Oscillator/DIVM WDT Oscillator/DIVMUndefined External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Uart ModesSFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsFraming Error Break DetectBrgcon Scon More about Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering Double Buffering in Different Modes9TH BIT BIT 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart Uart POWER-ON Reset Code Execution Block Diagram of ResetRstsrc Comparator Configuration Comparator and Power Reduction Modes Internal Reference VoltageComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbpatn KbconKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0Watchdog Timer in Timer Mode Prescaler Reset PclkWatchdog Control registerPower Down Operation Watchdog Clock SourcePrescaler CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVCA, @A+DPTR Move code byte relative to Dptr to the accumulatorMOVXA, @DPTR MOVX@DPTR, aFeatures Using Flash AS Data StorageGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Accessing Additional Flash Elements Assembly language routine to erase/program all or part of aERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 User Security Bytes SECxAddress xxxxh Unprogrammed value 00hBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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