Philips P89LPC908, P89LPC906, P89LPC907 user manual Fmcon

Page 91

Philips Semiconductors

 

 

 

 

 

 

 

 

 

 

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FLASH PROGRAM MEMORY

 

 

 

 

P89LPC906/907/908

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FMCON

 

 

7

 

6

 

5

 

4

 

3

 

2

1

 

0

 

 

Address: E4h

 

 

 

 

 

 

 

 

 

 

 

-

 

-

 

-

 

-

 

HVA

 

HVE

SV

 

OI

 

 

Not bit addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Source(s): Any reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FMCON.7-4

 

-

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FMCON.3

 

HVA

High voltage abort. Set if either an interrupt or a brown-out is detected during a program

 

 

 

or erase cycle. Also set if

the brown-out detector is disabled at the start of a program or

 

 

 

erase cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FMCON.2

 

HVE

High voltage error. Set when an error occurs in the high voltage generator.

 

 

 

FMCON.1

 

SV

Security violation. Set when an attempt is made to program, erase, or CRC a secured

 

 

 

sector or page.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FMCON.0

 

OI

Operation interrupted. Set when cycle aborted due to an interrupt or reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 14-1: Flash Memory Control Register

 

 

 

 

 

 

;* Inputs:

 

 

 

 

program (byte)

*

 

 

 

 

 

 

 

;*

R3 = number of bytes to

*

 

 

 

 

 

 

 

;*

R4 = page address MSB(byte)

 

 

 

 

*

 

 

 

 

 

 

 

;*

R5 = page address LSB(byte)

 

 

 

 

*

 

 

 

 

 

 

 

;*

R7 = pointer to data buffer in RAM(byte)

*

 

 

 

 

 

 

 

;* Outputs:

 

 

 

 

 

 

 

 

 

*

 

 

 

 

 

 

 

;*

R7 = status (byte)

set on error

 

 

*

 

 

 

 

 

 

 

;*

C = clear on no error,

 

 

*

 

 

 

 

 

 

 

LOAD

EQU

00H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EP

EQU

68H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM_USER:

FMCON,#LOAD

;load command, clears page register

 

 

 

 

MOV

 

 

 

 

MOV

FMADRH,R4

;get high address

 

 

 

 

 

 

 

 

 

MOV

FMADRL,R5

;get low address

 

 

 

 

 

 

 

 

 

MOV

A,R7

 

 

 

;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV

R0,A

 

 

 

;get pointer into R0

 

 

 

 

 

 

LOAD_PAGE:

FMDAT,@R0

;write data to page register

 

 

 

 

 

 

MOV

 

 

 

 

 

 

INC

R0

 

 

 

;point to next byte

 

 

 

 

 

 

 

 

 

DJNZ

R3,LOAD_PAGE

;do until count is zero

 

 

 

 

 

 

 

MOV

FMCON,#EP

;else erase & program the page

 

 

 

 

 

 

MOV

R7,FMCON

;copy status for return

 

 

 

 

 

 

 

MOV

A,R7

 

 

 

;read status

 

 

 

 

 

 

 

 

 

 

 

ANL

A,#0FH

 

 

 

;save only four lower bits

 

 

 

 

 

 

 

JNZ

BAD

 

 

 

;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR

C

 

 

 

;clear error flag if good

 

 

 

 

 

 

BAD:

RET

 

 

 

 

;and return

 

 

 

 

 

 

 

 

 

 

SETB

C

 

 

 

;set error flag

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RET

 

 

 

 

;and return

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2003 Dec 8

91

Page 90 Page 92
Image 91
Page 90 Page 92
Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsBreak Detect Framing ErrorBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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