Philips P89LPC908, P89LPC906 user manual PIN Descriptions P89LPC907, P1.0, TxD, P1.2

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Philips Semiconductors

 

 

 

User’s Manual - Preliminary -

 

 

 

 

 

 

GENERAL DESCRIPTION

P89LPC906/907/908

PIN DESCRIPTIONS - P89LPC907

 

 

 

 

 

 

 

 

 

Mnemonic

Pin no.

Type

Name and function

 

 

P0.4 - P0.6

3, 7,8

I/O

Port 0:

Port 0 is an I/O port with a user-configurable output types. During reset Port

 

 

 

 

0 latches are configured in the input only mode with the internal pullup

 

 

 

 

disabled. The operation of port 0 pins as inputs and outputs depends upon

 

 

 

 

the port configuration selected. Each port pin is configured independently.

 

 

 

 

Refer to the section Port Configurations on page 35 and the DC Electrical

 

 

 

 

Characteristics in the datasheet for details.

 

 

 

 

 

The Keypad Interrupt feature operates with port 0 pins.

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

Port 0 also provides various special functions as described below.

 

8

I/O

P0.4

Port 0 bit 4.

 

 

 

 

I

CIN1A

Comparator 1 positive input.

 

 

 

 

I

KBI4

Keyboard Input 4.

 

 

 

7

I/O

P0.5

Port 0 bit 5.

 

 

 

 

I

CMPREFComparator reference (negative) input.

 

 

 

 

I

KBI5

Keyboard Input 5.

 

 

 

3

I/O

P0.6

Port 0 bit 6.

 

 

 

 

O

CMP1

Comparator 1 output.

 

 

 

 

I

KBI6

Keyboard Input 6.

 

 

P1.0-P1.5

1,4,5

 

Port 1:

Port 1 is an I/O port with a user-configurable output types. During reset Port

 

 

 

 

1 latches are configured in the input only mode with the internal pull-up

 

 

 

 

disabled. The operation of the configurable port 1 pins as inputs and

 

 

 

 

outputs depends upon the port configuration selected. Each of the

 

 

 

 

configurable port pins are programmed independently. Refer to the section

 

 

 

 

Port Configurations on page 35 and the DC Electrical Characteristics in the

 

 

 

 

datasheet for details.

 

 

 

 

 

P1.5 is input only.

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

Port 1 also provides various special functions as described below.

 

5

I/O

P1.0

Port 1 bit 0.

 

 

 

 

O

TxD

Serial port transmitter data.

 

 

 

4

I/O

P1.2

Port 1 bit 2.

 

 

 

 

I/O

T0

Timer 0 external clock input, toggle output, PWM output.

 

1

I

P1.5

Port 1 bit 5. (Input only)

 

 

 

 

I

RST

External Reset input during power-on or if selected via UCFG1. When

 

 

 

 

functioning as a reset input a low on this pin resets the microcontroller,

 

 

 

 

causing I/O ports and peripherals to take on their default states, and the

 

 

 

 

processor begins execution at address 0. Also used during a power-on

 

 

 

 

sequence to force In-Circuit Programming mode.

VSS

2

I

Ground: 0V reference.

 

 

VDD

6

I

Power Supply: This is the power supply voltage for normal operation as well as Idle

 

 

 

and Power down modes.

 

 

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsKB Code Flash Block Diagram P89LPC906CPU Oscillator Divider Uart Block Diagram P89LPC907 Byte Data RAM ClockData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxDSpecial function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR CodeClock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionBIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterHigh freq LOW Power Select P89LPC906Med freq Low freqCPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RSTPort latch data Open Drain Output ConfigurationPUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC907 Port Output Configuration P89LPC906Port Output Configuration P89LPC908 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFnPclk TL0 Timer Overflow Toggle Output P89LPC907TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm CclkWDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVMChanging RTCS1-0 Reset Sources Affecting the REAL-TIME ClockREAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection Power Reduction Modes POWER-ON DetectionBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartBaud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsBreak Detect Framing ErrorBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesPrescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control registerWatchdog Clock Source Power Down OperationPrescaler CLKWatchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, aUsing Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsReading Additional Flash Elements ERASE-PROGRAMMING Additional Flash ElementsUCFG1 Fmadrl Conf UCFG1 User Configuration BytesP89LPC906 SECx User Security BytesAddress xxxxh Unprogrammed value 00hBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanB8-BF RetiD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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