Philips P89LPC906, P89LPC908, P89LPC907 user manual Wdcon

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Philips Semiconductors		User’s Manual - Preliminary -

WATCHDOG TIMER		P89LPC906/907/908
MOV	WFEED1,#0A5h	; do watchdog feed part 1
MOV	WFEED2,#05Ah	; do watchdog feed part 2
SETB	EA	; enable interrupt

In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle (no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.

WDCON

7

6

5

4

3

2

1

0

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

Address: A7h

Not bit addressable

Reset Source(s): See reset value below

Reset Value:

111xx1?1B

(Note: WDCON.7,6,5,2,0 - set to ’1’ any reset; WDCON.1 - cleared to ’0’ on Power-on

reset, set to ’1’ on watchdog reset, not affected by any other reset)

BIT

SYMBOL

FUNCTION

WDCON.7-5 PRE2-PRE0

Clock Prescaler Tap Select. Refer to Table for details.

WDCON.4-3

-

Reserved for future use. Should not be set to 1 by user program.

WDCON.2

WDRUN

Watchdog Run Control. The watchdog timer is started when WDRUN = 1 and stopped

when WDRUN = 0. This bit is forced to 1 (watchdog running) and cannot be cleared by

software if both WDTE and WDSE are set to 1.

WDCON.1

WDTOF

Watchdog Timer Time-Out Flag. This bit is set when the 8-bit down counter underflows.

In watchdog mode, a feed sequence will clear this bit. It can also be cleared by writing ’0’

to this bit in software.

WDCON.0

WDCLK

Watchdog input clock select. When set, the watchdog oscillator is selected. When cleared,

PCLK is selected. (If the CPU is powered down, the watchdog is disabled if WDCLK = 0,

see section "Power down operation"). (Note: If both WDTE and WDSE are set to 1, this bit is forced to 1.) Refer to section "Watchdog Clock Source" for details.

Figure 12-2: Watchdog Timer Control Register

The number of watchdog clocks before timing out is calculated by the following equations: tclks = (2(5+PRE) )(WDL+1)+1

where:

•PRE is the value of prescaler (PRE2-PRE0) which can be the range 0-7, and;

•WDL is the value of watchdog load register which can be the range of 0-255. The minimum number of tclks is:

tclks = (2(5+0))(0+1)+1 = 33 The maximum number of tclks is:

tclks = (2(5+7))(255+1)+1 = 1,048,577

The following table shows sample P89LPC906/907/908 timeout values.

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsKB Code Flash Block Diagram P89LPC906CPU Oscillator DividerUart Block Diagram P89LPC907Byte Data RAM ClockData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.0 PIN Descriptions P89LPC907TxD P1.2Keyboard Input P1.0 P1.5 PIN Descriptions P89LPC908P1.1 RxDSpecial function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Data Memory OrganizationSFR CodeClock Definitions Enhanced CPUCPU Clock Oscclk LOW Speed Oscillator Option P89LPC906Clock Output P89LPC906 Oscillator Option SELECTION- P89LPC906ON-CHIP RC Oscillator Option Watchdog Oscillator OptionBIT Symbol Function CPU Clock Cclk Wakeup DelayExternal Clock Input Option P89LPC906 CPU Clock Cclk Modification Divm RegisterHigh freq LOW Power Select P89LPC906Med freq Low freqCPU Clocks Interrupt Priority Structure Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC906 Description Interrupt ArbitrationExternal Interrupt PIN Glitch Suppression External Interrupt InputsSummary of Interrupts P89LPC907,P89LPC908 Description TI & RIBopd EBO Rtcf Kbif Interrupts QUASI-BIDIRECTIONAL Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RSTPort latch data Open Drain Output ConfigurationPUSH-PULL Output Configuration INPUT-ONLY ConfigurationPort 0 Analog Functions Strong Port latch data Port pin Input data Glitch rejectionPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.7 TmodTMOD.6 TMOD.3Mode Overflows. ModeTamod P89LPC907 TAMOD.7-1Tcon T0C/T = Overflow TLn THn TFn Interrupt T0 Pin PclkT0C/T = Overflow THn TFnTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency FOSC2 FOSC1 FOSC0 RTCS10Xclk Divm CclkWDT Oscillator/DIVM RC Oscillator/DIVMUndefined External clock/DIVMReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartBaud Rate Generator and Selection SFR SpaceUpdating the BRGR1 and BRGR0 Sfrs SFR Locations for UARTsFraming Error Break DetectBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =More about Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration Internal Reference Voltage Comparator and Power Reduction ModesComparator Interrupt CIN1A CO1 CMP1 CmprefComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesPrescaler Reset Pclk Watchdog Timer in Timer ModeWatchdog Control registerWatchdog Clock Source Power Down OperationPrescaler CLKWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 Move code byte relative to Dptr to the accumulator MOVCA, @A+DPTRMOVXA, @DPTR MOVX@DPTR, aUsing Flash AS Data Storage FeaturesGeneral Description Introduction to IAP-LITEFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 SECx User Security BytesAddress xxxxh Unprogrammed value 00hBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanB8-BF RetiD8-DF Miscellaneous2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908