Philips P89LPC906, P89LPC908, P89LPC907 user manual More about Uart Mode, Sstat

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Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

UART

P89LPC906/907/908

 

SSTAT

Address: BAh

Not bit addressable

Reset Source(s): Any reset

Reset Value: 00000000B

7

6

5

4

3

2

1

0

DBMOD

INTLO

CIDIS

DBISEL

FE

BR

OE

STINT

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

SSTAT.7

DBMOD

Double buffering mode. When set = 1 enables double buffering. Must be ’0’ for UART

 

 

mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to

 

 

disable double buffering.

SSTAT.6

INTLO

Transmit interrupt position. When cleared = 0, the Tx interrupt is issued at the beginning

 

 

of the stop bit. When set =1, the Tx interrupt is issued at end of the stop bit. Must be ’0’

 

 

for mode 0. Note that in the case of single buffering, if the Tx interrupt occurs at the end

 

 

of a STOP bit, a gap may exist before the next start bit.

SSTAT.5

CIDIS

Combined Interrupt Disable. When set = 1, Rx and Tx interrupts are separate. When

 

 

cleared = 0, the UART uses a combined Tx/Rx interrupt (like a conventional 80C51

 

 

UART). This bit is reset to ’0’ to select combined interrupts.

SSTAT.4

DBISEL

Double buffering transmit interrupt select. Used only if double buffering is enabled.This bit

 

 

controls the number of interrupts that can occur when double buffering is enabled. When

 

 

set, one transmit interrupt is generated after each character written to SBUF, and there is

 

 

also one more transmit interrupt generated at the beginning (INTLO = 0) or the end

 

 

(INTLO = 1) of the STOP bit of the last character sent (i.e., no more data in buffer). This

 

 

last interrupt can be used to indicate that all transmit operations are over. When cleared

 

 

= 0, only one transmit interrupt is generated per character written to SBUF. Must be ’0’

 

 

when double buffering is disabled.

 

 

Note that except for the first character written (when buffer is empty), the location of the

 

 

transmit interrupt is determined by INTLO. When the first character is written, the transmit

 

 

interrupt is generated immediately after SBUF is written.

SSTAT.3

FE

Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the

 

 

frame. Cleared by software.

SSTAT.2

BR

Break Detect flag. A break is detected when any 11 consecutive bits are sensed low.

 

 

Cleared by software.

SSTAT.1

OE

Overrun Error flag is set if a new character is received in the receiver buffer while it is still

 

 

full (before the software has read the previous character from the buffer), i.e., when bit 8

 

 

of a new byte is received while RI in SCON is still set. Cleared by software.

SSTAT.0

STINT

Status Interrupt Enable. When set =1, FE, BR, or OE can cause an interrupt. The

 

 

interrupt used (vector address 0023h) is shared with RI (CIDIS = 1) or the combined TI/RI

 

 

(CIDIS = 0). When cleared = 0, FE, BR, OE cannot cause an interrupt. (Note: FE, BR, or

 

 

OE is often accompanied by a RI, which will generate an interrupt regardless of the state

 

 

of STINT). Note that BR can cause a break detect reset if EBRR (AUXR1.6) is set to ’1’.

Figure 8-4: Serial Port Status Register (SSTAT)

MORE ABOUT UART MODE 0

In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI (SCON.1) is set, which must be cleared in software. Double buffering must be disabled in this mode.

Reception is initiated by clearing RI (SCON.0). Synchronous serial transfer occurs and RI will be set again at the end of the transfer. When RI is cleared, the reception of the next character will begin. Refer to Figure 8-5 for timing.

2003 Dec 8

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Contents User Manual Table of Contents Power-On reset code execution Brownout Detection Power-On Detection Power Reduction Modes103 List of Figures List of Figures P89LPC906 PIN ConfigurationsProduct Comparison Logic SymbolsOscillator Divider Block Diagram P89LPC906KB Code Flash CPUClock Block Diagram P89LPC907Uart Byte Data RAMData RAM Port Block Diagram P89LPC908PIN Descriptions P89LPC906 P1.2 PIN Descriptions P89LPC907P1.0 TxDRxD PIN Descriptions P89LPC908Keyboard Input P1.0 P1.5 P1.1Special function registers table P89LPC906 Special function registersMSB LSB Hex Special function registers table P89LPC907 CMP1 Cmpref TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Special function registers table P89LPC908 KB2 KB6 KB5 KB4 TL0 Code Memory OrganizationData SFRLOW Speed Oscillator Option P89LPC906 Enhanced CPUClock Definitions CPU Clock OscclkWatchdog Oscillator Option Oscillator Option SELECTION- P89LPC906Clock Output P89LPC906 ON-CHIP RC Oscillator OptionCPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayBIT Symbol Function External Clock Input Option P89LPC906Low freq LOW Power Select P89LPC906High freq Med freqCPU Clocks Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingInterrupt Priority Structure Summary of Interrupts P89LPC906 DescriptionTI & RI External Interrupt InputsExternal Interrupt PIN Glitch Suppression Summary of Interrupts P89LPC907,P89LPC908 DescriptionBopd EBO Rtcf Kbif Interrupts RST Port ConfigurationsQUASI-BIDIRECTIONAL Output Configuration Number of I/O Pins Available Clock Source Reset OptionPort latch data Open Drain Output ConfigurationStrong Port latch data Port pin Input data Glitch rejection INPUT-ONLY ConfigurationPUSH-PULL Output Configuration Port 0 Analog FunctionsPort Output Configuration P89LPC906 Port Output Configuration P89LPC907Port Output Configuration P89LPC908 Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.7-1 Overflows. ModeMode Tamod P89LPC907Tcon THn TFn PclkT0C/T = Overflow TLn THn TFn Interrupt T0 Pin T0C/T = OverflowTimer Overflow Toggle Output P89LPC907 Pclk TL0TR0 ENT0 Pclk TH0 Timers 0 REAL-TIME Clock Source Divm Cclk FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkExternal clock/DIVM RC Oscillator/DIVMWDT Oscillator/DIVM UndefinedReset Sources Affecting the REAL-TIME Clock Changing RTCS1-0REAL-TIME Clock INTERRUPT/WAKE UP Rtccon REAL-TIME CLOCK/SYSTEM Timer Brownout Detection POWER-ON Detection Power Reduction ModesBrownout Options Power Reduction Modes Pcon Pcona Power Monitoring Functions Modes UartSFR Locations for UARTs SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SfrsFraming Error Break DetectBrgcon Scon Sstat More about Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 More about Uart Modes 2Double Buffering in Different Modes Double BufferingTransmission with and without Double Buffering 9TH BIT BIT 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart Uart Block Diagram of Reset POWER-ON Reset Code ExecutionRstsrc Comparator Configuration CIN1A CO1 CMP1 Cmpref Comparator and Power Reduction ModesInternal Reference Voltage Comparator InterruptComparator Configuration Example Analog Comparators Kbcon KbpatnKbmask Watchdog timer configuration Watchdog FunctionWdte Wdse Function Feed Sequence Wdcon PRE2-PRE0 P89LPC906/907/908 Watchdog Timeout ValuesControl register Watchdog Timer in Timer ModePrescaler Reset Pclk WatchdogCLK Power Down OperationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Software Reset Dual Data PointersAUXR1 MOVX@DPTR, a MOVCA, @A+DPTRMove code byte relative to Dptr to the accumulator MOVXA, @DPTRIntroduction to IAP-LITE FeaturesUsing Flash AS Data Storage General DescriptionFlash Program Memory Fmcon Assembly language routine to erase/program all or part of a Accessing Additional Flash ElementsERASE-PROGRAMMING Additional Flash Elements Reading Additional Flash ElementsUCFG1 Fmadrl Conf User Configuration Bytes UCFG1P89LPC906 Unprogrammed value 00h User Security BytesSECx Address xxxxhBootstat BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DF2003 Dec Initial release 104 Index Dual Data Pointers Port 0 12, 13 SFR 109 P89LPC906/907/908
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